diff options
author | Varadarajan Narayanan <varada@codeaurora.org> | 2016-03-02 16:57:10 +0530 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2016-05-10 21:34:21 +0200 |
commit | a6935c2508c426f30d6bf5bcf4c3130277a0f998 (patch) | |
tree | e844bb803e8c069101fdf6ec47017af9dc832713 /src/soc/qualcomm/ipq40xx/gsbi.c | |
parent | c84e2fe893e02de3c5d97d26d05462351ac90d91 (diff) | |
download | coreboot-a6935c2508c426f30d6bf5bcf4c3130277a0f998.tar.xz |
soc/qualcomm/ipq40xx: Initial commit for IPQ40xx SoC support
Copy 'ipq806x' files as a template
BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none
Original-Commit-Id: dc6a5937953fe61cd4b5a99ca49f9371c4b712d4
Original-Change-Id: If171fcdd3b0561cb6b7dab5f8434de7ef711ea41
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Signed-off-by: Kan Yan <kyan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/333178
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
squashed:
soc/qualcomm/ipq40xx: Update ipq806x/storm references
Since the files were taken from ipq806x/storm as
template. Update those references to reflect
ipq40xx/gale.
BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none
Original-Commit-Id: c6c76d184cc92c09e6826fbdc7d7fac59b2cb69b
Original-Change-Id: Ieae1bce25291243b4a6034d37a6949978f318997
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333293
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ie5794c48131ae562861074b406106734541880d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14644
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/qualcomm/ipq40xx/gsbi.c')
-rw-r--r-- | src/soc/qualcomm/ipq40xx/gsbi.c | 109 |
1 files changed, 109 insertions, 0 deletions
diff --git a/src/soc/qualcomm/ipq40xx/gsbi.c b/src/soc/qualcomm/ipq40xx/gsbi.c new file mode 100644 index 0000000000..98c4edd084 --- /dev/null +++ b/src/soc/qualcomm/ipq40xx/gsbi.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 - 2015 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch/io.h> +#include <soc/iomap.h> +#include <soc/gsbi.h> +#include <console/console.h> + +static inline void *gsbi_ctl_reg_addr(gsbi_id_t gsbi_id) +{ + switch (gsbi_id) { + case GSBI_ID_1: + return GSBI1_CTL_REG; + case GSBI_ID_2: + return GSBI2_CTL_REG; + case GSBI_ID_3: + return GSBI3_CTL_REG; + case GSBI_ID_4: + return GSBI4_CTL_REG; + case GSBI_ID_5: + return GSBI5_CTL_REG; + case GSBI_ID_6: + return GSBI6_CTL_REG; + case GSBI_ID_7: + return GSBI7_CTL_REG; + default: + printk(BIOS_ERR, "Unsupported GSBI%d\n", gsbi_id); + return 0; + } +} + +gsbi_return_t gsbi_init(gsbi_id_t gsbi_id, gsbi_protocol_t protocol) +{ + unsigned reg_val; + unsigned m = 1; + unsigned n = 4; + unsigned pre_div = 4; + unsigned src = 3; + unsigned mnctr_mode = 2; + void *gsbi_ctl = gsbi_ctl_reg_addr(gsbi_id); + + if (!gsbi_ctl) + return GSBI_ID_ERROR; + + write32(GSBI_HCLK_CTL(gsbi_id), + (1 << GSBI_HCLK_CTL_GATE_ENA) | + (1 << GSBI_HCLK_CTL_BRANCH_ENA)); + + if (gsbi_init_board(gsbi_id)) + return GSBI_UNSUPPORTED; + + write32(GSBI_QUP_APSS_NS_REG(gsbi_id), 0); + write32(GSBI_QUP_APSS_MD_REG(gsbi_id), 0); + + reg_val = ((m & GSBI_QUP_APPS_M_MASK) << GSBI_QUP_APPS_M_SHFT) | + ((~n & GSBI_QUP_APPS_D_MASK) << GSBI_QUP_APPS_D_SHFT); + write32(GSBI_QUP_APSS_MD_REG(gsbi_id), reg_val); + + reg_val = (((~(n - m)) & GSBI_QUP_APPS_N_MASK) << + GSBI_QUP_APPS_N_SHFT) | + ((mnctr_mode & GSBI_QUP_APPS_MNCTR_MODE_MSK) << + GSBI_QUP_APPS_MNCTR_MODE_SFT) | + (((pre_div - 1) & GSBI_QUP_APPS_PRE_DIV_MSK) << + GSBI_QUP_APPS_PRE_DIV_SFT) | + (src & GSBI_QUP_APPS_SRC_SEL_MSK); + write32(GSBI_QUP_APSS_NS_REG(gsbi_id), reg_val); + + reg_val |= (1 << GSBI_QUP_APPS_ROOT_ENA_SFT) | + (1 << GSBI_QUP_APPS_MNCTR_EN_SFT); + write32(GSBI_QUP_APSS_NS_REG(gsbi_id), reg_val); + + reg_val |= (1 << GSBI_QUP_APPS_BRANCH_ENA_SFT); + write32(GSBI_QUP_APSS_NS_REG(gsbi_id), reg_val); + + /*Select i2c protocol*/ + write32(gsbi_ctl, + ((GSBI_CTL_PROTO_I2C & GSBI_CTL_PROTO_CODE_MSK) + << GSBI_CTL_PROTO_CODE_SFT)); + + return GSBI_SUCCESS; +} |