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| author | Varadarajan Narayanan <varada@codeaurora.org> | 2016-02-01 11:36:51 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-05-10 23:19:46 +0200 |
| commit | a86a1837d25d5b2f6737a532611b8d974134d60f (patch) | |
| tree | 4914d8679937c48dedd434f1eec1bf1925fea0ce /src/soc/qualcomm/ipq40xx | |
| parent | 520d5fb4272e8f80aef9904dc06c5c5083799d9b (diff) | |
| download | coreboot-a86a1837d25d5b2f6737a532611b8d974134d60f.tar.xz | |
soc/qualcomm/ipq40xx: Update memory region areas
This file had the memory regions applicable to ipq806x.
Update the regions as applicable to ipq40xx.
BUG=chrome-os-partner:49249
TEST=Able to boot on DK04 board
BRANCH=none
Change-Id: I0d782eb70fd62c6bf92f9fac39d2e42e9af82012
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e6a088c2666cf5be52358bb4271b45cb65d11f7c
Original-Change-Id: I4fb3ca7fb168813d8871bfb87d475fd09d1a9d97
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333310
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/14670
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/ipq40xx')
| -rw-r--r-- | src/soc/qualcomm/ipq40xx/soc.c | 38 |
1 files changed, 33 insertions, 5 deletions
diff --git a/src/soc/qualcomm/ipq40xx/soc.c b/src/soc/qualcomm/ipq40xx/soc.c index 201e9bc9fe..4889f8cc6a 100644 --- a/src/soc/qualcomm/ipq40xx/soc.c +++ b/src/soc/qualcomm/ipq40xx/soc.c @@ -20,14 +20,42 @@ #include <symbols.h> #include <soc/ipq_uart.h> -#define RESERVED_SIZE_KB (0x01500000 / KiB) +typedef struct { + uint8_t hlos1[112 * MiB], /* <-- 0x80000000 */ + appsbl[4 * MiB], /* <-- 0x87000000 */ + sbl[1 * MiB], /* <-- 0x87400000 */ + rsvd[11 * MiB], /* <-- 0x87500000 */ + hlos2[128 * MiB]; /* <-- 0x88000000 */ +} ipq_mem_map_t; + +#define LINUX_REGION1_START ((uintptr_t)(ipq_mem_map->hlos1)) +#define LINUX_REGION1_START_KB (LINUX_REGION1_START / KiB) +#define LINUX_REGION1_SIZE (sizeof(ipq_mem_map->hlos1) + \ + sizeof(ipq_mem_map->appsbl) + \ + sizeof(ipq_mem_map->sbl)) +#define LINUX_REGION1_SIZE_KB (LINUX_REGION1_SIZE / KiB) + +#define RESERVED_START ((uintptr_t)(ipq_mem_map->rsvd)) +#define RESERVED_START_KB (RESERVED_START / KiB) +#define RESERVED_SIZE (sizeof(ipq_mem_map->rsvd)) +#define RESERVED_SIZE_KB (RESERVED_SIZE / KiB) + +/* xxx_SIZE defines not needed since it goes till end of memory */ +#define LINUX_REGION2_START ((uintptr_t)(ipq_mem_map->hlos2)) +#define LINUX_REGION2_START_KB (LINUX_REGION2_START / KiB) static void soc_read_resources(device_t dev) { - /* Reserve bottom 0x150_0000 bytes for NSS, SMEM, etc. */ - reserved_ram_resource(dev, 0, (uintptr_t)_dram / KiB, RESERVED_SIZE_KB); - ram_resource(dev, 0, (uintptr_t)_dram / KiB + RESERVED_SIZE_KB, - (CONFIG_DRAM_SIZE_MB * KiB) - RESERVED_SIZE_KB); + ipq_mem_map_t *ipq_mem_map = ((ipq_mem_map_t *)_dram); + + ram_resource(dev, 0, LINUX_REGION1_START_KB, LINUX_REGION1_SIZE_KB); + + reserved_ram_resource(dev, 1, RESERVED_START_KB, RESERVED_SIZE_KB); + + /* 0x88000000 to end, is the second region for Linux */ + ram_resource(dev, 2, LINUX_REGION2_START_KB, + (CONFIG_DRAM_SIZE_MB * KiB) - + LINUX_REGION1_SIZE_KB - RESERVED_SIZE_KB); } static void soc_init(device_t dev) |