Change all clrsetbits_leXX() to clrsetbitsXX()

This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.

This patch was created by running

 sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'

across the codebase and cleaning up formatting a bit.

Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

4 files changed, 15 insertions, 15 deletions

diff --git a/src/soc/qualcomm/ipq40xx/blsp.c b/src/soc/qualcomm/ipq40xx/blsp.c
index 75618c2461..099dc6e2c1 100644
--- a/src/soc/qualcomm/ipq40xx/blsp.c
+++ b/src/soc/qualcomm/ipq40xx/blsp.c
@@ -47,7 +47,7 @@ blsp_return_t blsp_i2c_init(blsp_qup_id_t id)
 		return BLSP_UNSUPPORTED;
 
 	/* Configure Mini core to I2C core */
-	clrsetbits_le32(base, BLSP_MINI_CORE_MASK, BLSP_MINI_CORE_I2C);
+	clrsetbits32(base, BLSP_MINI_CORE_MASK, BLSP_MINI_CORE_I2C);
 
 	return BLSP_SUCCESS;
 }
diff --git a/src/soc/qualcomm/ipq40xx/clock.c b/src/soc/qualcomm/ipq40xx/clock.c
index e3d60e4749..bd1345e4ac 100644
--- a/src/soc/qualcomm/ipq40xx/clock.c
+++ b/src/soc/qualcomm/ipq40xx/clock.c
@@ -59,7 +59,7 @@ void uart_clock_config(unsigned int blsp_uart, unsigned int m,
 			2 << 12);	/* 13:12 Mode = Dual Edge */
 
 	/* Trigger update */
-	setbits_le32(GCC_BLSP1_UART_APPS_CMD_RCGR(blsp_uart), 1);
+	setbits32(GCC_BLSP1_UART_APPS_CMD_RCGR(blsp_uart), 1);
 
 	/* Wait for update */
 	for (i = 0; i < CLOCK_UPDATE_DELAY; i++) {
@@ -71,7 +71,7 @@ void uart_clock_config(unsigned int blsp_uart, unsigned int m,
 	}
 
 	/* Please refer to the comments in blsp_i2c_clock_config() */
-	setbits_le32(GCC_CLK_BRANCH_ENA, BLSP1_AHB | BLSP1_SLEEP);
+	setbits32(GCC_CLK_BRANCH_ENA, BLSP1_AHB | BLSP1_SLEEP);
 }
 
 /**
@@ -154,7 +154,7 @@ int blsp_i2c_clock_config(blsp_qup_id_t id)
 	 * the same bits is harmless. Hence repeating them here should be ok.
 	 * This will ensure root and branch clocks remain on.
 	 */
-	setbits_le32(GCC_CLK_BRANCH_ENA, BLSP1_AHB | BLSP1_SLEEP);
+	setbits32(GCC_CLK_BRANCH_ENA, BLSP1_AHB | BLSP1_SLEEP);
 
 	/* Src Sel 1 (fepll 200), Src Div 10.5 */
 	write32(clk[id].cfg, (1u << 8) | (20u << 0));
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
index 930c912ee6..e4b613f7dc 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
+++ b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
@@ -47,8 +47,8 @@
  */
 #define readl_i(a)           read32((const void *)(a))
 #define writel_i(v,a)        write32((void *)a, v)
-#define clrsetbits_le32_i(addr, clear, set)  \
-	clrsetbits_le32(((void *)(addr)), (clear), (set))
+#define clrsetbits32_i(addr, clear, set)  \
+	clrsetbits32(((void *)(addr)), (clear), (set))
 
 #define GCC_CLK_CTL_REG			((void *)0x01800000u)
 #define MSM_CLK_CTL_BASE		GCC_CLK_CTL_REG
diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c
index b68e1cb864..3b0d63603d 100644
--- a/src/soc/qualcomm/ipq40xx/spi.c
+++ b/src/soc/qualcomm/ipq40xx/spi.c
@@ -240,7 +240,7 @@ static int spi_hw_init(struct ipq_spi_slave *ds)
 	 * Configure Mini core to SPI core with Input Output enabled,
 	 * SPI master, N = 8 bits
 	 */
-	clrsetbits_le32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK |
+	clrsetbits32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK |
 						QUP_CONF_INPUT_MSK |
 						QUP_CONF_OUTPUT_MSK |
 						QUP_CONF_N_MASK,
@@ -253,7 +253,7 @@ static int spi_hw_init(struct ipq_spi_slave *ds)
 	 * Configure Input first SPI protocol,
 	 * SPI master mode and no loopback
 	 */
-	clrsetbits_le32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK |
+	clrsetbits32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK |
 						SPI_CONFIG_NO_SLAVE_OPER_MSK,
 						SPI_CONFIG_NO_LOOP_BACK |
 						SPI_CONFIG_NO_SLAVE_OPER);
@@ -273,7 +273,7 @@ static int spi_hw_init(struct ipq_spi_slave *ds)
 	 * INPUT_MODE = Block Mode
 	 * OUTPUT MODE = Block Mode
 	 */
-	clrsetbits_le32(ds->regs->qup_io_modes,
+	clrsetbits32(ds->regs->qup_io_modes,
 				QUP_IO_MODES_OUTPUT_BIT_SHIFT_MSK |
 				QUP_IO_MODES_INPUT_MODE_MSK |
 				QUP_IO_MODES_OUTPUT_MODE_MSK,
@@ -320,10 +320,10 @@ static void write_force_cs(const struct spi_slave *slave, int assert)
 	struct ipq_spi_slave *ds = to_ipq_spi(slave);
 
 	if (assert)
-		clrsetbits_le32(ds->regs->io_control,
+		clrsetbits32(ds->regs->io_control,
 			SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_EN);
 	else
-		clrsetbits_le32(ds->regs->io_control,
+		clrsetbits32(ds->regs->io_control,
 			SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_DIS);
 
 	return;
@@ -385,18 +385,18 @@ static void enable_io_config(struct ipq_spi_slave *ds,
 {
 
 	if (write_cnt) {
-		clrsetbits_le32(ds->regs->qup_config,
+		clrsetbits32(ds->regs->qup_config,
 				QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA);
 	} else {
-		clrsetbits_le32(ds->regs->qup_config,
+		clrsetbits32(ds->regs->qup_config,
 				QUP_CONF_OUTPUT_MSK, QUP_CONF_NO_OUTPUT);
 	}
 
 	if (read_cnt) {
-		clrsetbits_le32(ds->regs->qup_config,
+		clrsetbits32(ds->regs->qup_config,
 				QUP_CONF_INPUT_MSK, QUP_CONF_INPUT_ENA);
 	} else {
-		clrsetbits_le32(ds->regs->qup_config,
+		clrsetbits32(ds->regs->qup_config,
 				QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT);
 	}