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| author | Jacob Garber <jgarber1@ualberta.ca> | 2019-07-24 11:12:09 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-19 09:28:10 +0000 |
| commit | 783982751d26161bb1cb0d923375fabd92940a0f (patch) | |
| tree | 35b7ea01eaeb9049d78b6aeadf1de8d9614c6d53 /src/soc/qualcomm/ipq40xx | |
| parent | e30a0e63b5285bb84ce7cdce5d0c9aabba32c536 (diff) | |
| download | coreboot-783982751d26161bb1cb0d923375fabd92940a0f.tar.xz | |
cpu,mb,soc: Init missing lb_serial struct fields
Initialize the input_hertz and uart_pci_addr fields of the lb_serial
struct to prevent later undefined reads in lb_add_serial(). This was
done for exynos5420 in commit ff94e00362 (soc/samsung/exynos5420/uart.c:
Init new serial struct variables), and this patch finishes the rest.
Note that not all of the drivers can have the UART PCI address
configured at build time, so a follow-up patch will be needed to correct
those ones.
Change-Id: I733bc8185e2f2d28a9823495b53d6b09dce4deb1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1354778
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34548
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/ipq40xx')
| -rw-r--r-- | src/soc/qualcomm/ipq40xx/uart.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index 95e2eab16d..6e5bac624b 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -292,7 +292,9 @@ void uart_fill_lb(void *data) serial.baseaddr = (uint32_t)UART1_DM_BASE; serial.baud = get_uart_baudrate(); serial.regwidth = 1; - + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } |