summaryrefslogtreecommitdiff
path: root/src/soc/qualcomm/ipq806x/Makefile.inc
diff options
context:
space:
mode:
authorVadim Bendebury <vbendeb@chromium.org>2015-02-11 15:13:04 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-17 09:59:35 +0200
commit3cfb6a066b6801186b716a4f789b69655e1e420e (patch)
tree26e16a9a74e4819bdac5e286fdd70d4953ed92ad /src/soc/qualcomm/ipq806x/Makefile.inc
parent7f70ad610b23ef389c73b61a73d0920b77da4460 (diff)
downloadcoreboot-3cfb6a066b6801186b716a4f789b69655e1e420e.tar.xz
ipq806x: add LPASS clock control driver
Add a clock control driver to initialize the clock tree inside the low-power audio subsystem. Depthcharge builds up on this to enable audio function on storm. The clock is hardcoded for 48KHz frame rate, two 16 bit channels. BRANCH=storm BUG=chrome-os-partner:35247 TEST=with depthcharge patches applied and Using depthcharge CLI audio test program verified that the target generates sensible sounds audio 100 100 audio 1000 5000 Change-Id: I56513fc782657ade99b6e43b2d5d3141d27ecc4e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0d4f408408aa38b2f0ee19b83ed490de39074760 Original-Change-Id: If8ffc326698fcea17e05d536930d927ca553481f Original-Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/248830 Original-Reviewed-by: Dylan Reid <dgreid@chromium.org> Reviewed-on: http://review.coreboot.org/9758 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/ipq806x/Makefile.inc')
-rw-r--r--src/soc/qualcomm/ipq806x/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc
index e0f014af35..80bd0587b1 100644
--- a/src/soc/qualcomm/ipq806x/Makefile.inc
+++ b/src/soc/qualcomm/ipq806x/Makefile.inc
@@ -44,6 +44,7 @@ ramstage-y += blobs_init.c
ramstage-y += cbmem.c
ramstage-y += clock.c
ramstage-y += gpio.c
+ramstage-y += lcc.c
ramstage-y += soc.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c
ramstage-y += timer.c