diff options
| author | Julius Werner <jwerner@chromium.org> | 2014-05-30 18:01:44 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-01-04 00:15:17 +0100 |
| commit | 028cba9266e531d9d7c5e39432bbb7eeda6398ed (patch) | |
| tree | 20e7c32ea7fb9c1d676790a2b8f20f7a0bf45f03 /src/soc/qualcomm/ipq806x/clock.c | |
| parent | 96ef1883a7a8b95f297f99fa7409f27c0f344d88 (diff) | |
| download | coreboot-028cba9266e531d9d7c5e39432bbb7eeda6398ed.tar.xz | |
ipq806x: Add USB support
This patch adds code to initialize the two DWC3 USB host controllers and
their associated PHYs to the IPQ806x SoC (closely imitating the existing
DWC3 implementation for Exynos5), and uses them to initialize USB on the
Storm mainboard.
BUG=chrome-os-partner:29375
TEST=Hack up netboot to get around missing SPI flash, load a file over
TFTP. Hack a storage read into the storage attach function, dump the
data and confirm that it looks right. Enable USB debugging and confirm
3.0 devices get enumerated at SuperSpeed (mostly).
Original-Change-Id: Iaf7b96bef994081ca222b7de9d8e8c49751d3f1d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202157
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit 6349e7281d5accb1247acb0537a48fa3a5e1bf97)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I749d265d45c6a807a7559bd4df2490a6eb8067af
Reviewed-on: http://review.coreboot.org/8056
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/ipq806x/clock.c')
| -rw-r--r-- | src/soc/qualcomm/ipq806x/clock.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/soc/qualcomm/ipq806x/clock.c b/src/soc/qualcomm/ipq806x/clock.c index 70afcec419..88056d4923 100644 --- a/src/soc/qualcomm/ipq806x/clock.c +++ b/src/soc/qualcomm/ipq806x/clock.c @@ -118,3 +118,29 @@ void nand_clock_config(void) /* Wait for clock to stabilize. */ udelay(10); } + +/** + * usb_clock_config - configure USB controller clocks and reset the controller + */ +void usb_clock_config(void) +{ + /* Magic clock initialization numbers, nobody knows how they work... */ + write32(0x10, USB30_MASTER_CLK_CTL_REG); + write32(0x10, USB30_1_MASTER_CLK_CTL_REG); + write32(0x500DF, USB30_MASTER_CLK_MD); + write32(0xE40942, USB30_MASTER_CLK_NS); + write32(0x100D7, USB30_MOC_UTMI_CLK_MD); + write32(0xD80942, USB30_MOC_UTMI_CLK_NS); + write32(0x10, USB30_MOC_UTMI_CLK_CTL); + write32(0x10, USB30_1_MOC_UTMI_CLK_CTL); + + write32(1 << 5 | /* assert port2 HS PHY async reset */ + 1 << 4 | /* assert master async reset */ + 1 << 3 | /* assert sleep async reset */ + 1 << 2 | /* assert MOC UTMI async reset */ + 1 << 1 | /* assert power-on async reset */ + 1 << 0 | /* assert PHY async reset */ + 0, USB30_RESET); + udelay(5); + write32(0, USB30_RESET); /* deassert all USB resets again */ +} |