diff options
author | Vadim Bendebury <vbendeb@chromium.org> | 2014-04-08 18:45:46 -0700 |
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committer | Marc Jones <marc.jones@se-eng.com> | 2014-11-12 20:39:13 +0100 |
commit | 476f7316a1e2596cc5c3e83d05003203a042a4eb (patch) | |
tree | 8a7a3834ab6617ae9c511fa039f7f198c40163d0 /src/soc/qualcomm/ipq806x/clock.c | |
parent | 9cb70ae31f482f45ffeeae7008edca8978730926 (diff) | |
download | coreboot-476f7316a1e2596cc5c3e83d05003203a042a4eb.tar.xz |
Copy u-boot sources as is and modify the tree to still build
This patch brings in ipq806x source files from the vendor's u-boot
tree as it was published in the 'cs_banana' release.
The following files are being copied:
arch/arm/cpu/armv7/ipq/clock.c => src/soc/qualcomm/ipq806x/clock.c
arch/arm/cpu/armv7/ipq/gpio.c => src/soc/qualcomm/ipq806x/gpio.c
arch/arm/cpu/armv7/ipq/timer.c => src/soc/qualcomm/ipq806x/timer.c
arch/arm/include/asm/arch-ipq806x/clock.h => src/soc/qualcomm/ipq806x/clock.h
arch/arm/include/asm/arch-ipq806x/gpio.h => src/soc/qualcomm/ipq806x/gpio.h
arch/arm/include/asm/arch-ipq806x/gsbi.h => src/soc/qualcomm/ipq806x/gsbi.h
arch/arm/include/asm/arch-ipq806x/iomap.h => src/soc/qualcomm/ipq806x/iomap.h
arch/arm/include/asm/arch-ipq806x/timer.h src/soc/qualcomm/ipq806x/timer.h
arch/arm/include/asm/arch-ipq806x/uart.h => src/soc/qualcomm/ipq806x/uart.h
board/qcom/ipq806x_cdp/ipq806x_cdp.c => src/mainboard/google/storm/cdp.c
board/qcom/ipq806x_cdp/ipq806x_cdp.h => src/soc/qualcomm/ipq8064/cdp.h
drivers/serial/ipq806x_uart.c => src/console/ipq806x_console.c
Note that local timer.c gets overwritten with the original version. To
prevent a build breakage some shortly to be reverted modifications had
to be made to src/soc/qualcomm/ipq806x/Makefile.inc and
src/soc/qualcomm/ipq806x/cbfs.c.
BRANCH=none
BUG=chrome-os-partner:27784
TEST='emerge-storm coreboot' still succeeds
Original-Change-Id: I3f50bfbec2e18a3b5d2c640cff353a26f88c98c1
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/193722
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 3c9c2ede7e97e330cad2c2f3e557cc9bcdaecdcc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ia7bc66cecfc16f1dd4a9f3cb9840cbe91878adf4
Reviewed-on: http://review.coreboot.org/7263
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/ipq806x/clock.c')
-rw-r--r-- | src/soc/qualcomm/ipq806x/clock.c | 123 |
1 files changed, 123 insertions, 0 deletions
diff --git a/src/soc/qualcomm/ipq806x/clock.c b/src/soc/qualcomm/ipq806x/clock.c new file mode 100644 index 0000000000..882be02f9f --- /dev/null +++ b/src/soc/qualcomm/ipq806x/clock.c @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved. + */ + +#include <common.h> +#include <asm/arch-ipq806x/clock.h> +#include <asm/arch-ipq806x/nss/clock.h> +#include <asm/arch-ipq806x/iomap.h> +#include <asm/io.h> + +/** + * uart_pll_vote_clk_enable - enables PLL8 + */ +void uart_pll_vote_clk_enable(unsigned int clk_dummy) +{ + setbits_le32(BB_PLL_ENA_SC0_REG, BIT(8)); + + if (!clk_dummy) + while((readl(PLL_LOCK_DET_STATUS_REG) & BIT(8)) == 0); +} + +/** + * uart_set_rate_mnd - configures divider M and D values + * + * Sets the M, D parameters of the divider to generate the GSBI UART + * apps clock. + */ +static void uart_set_rate_mnd(unsigned int gsbi_port, unsigned int m, + unsigned int n) +{ + /* Assert MND reset. */ + setbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7)); + /* Program M and D values. */ + writel(MD16(m, n), GSBIn_UART_APPS_MD_REG(gsbi_port)); + /* Deassert MND reset. */ + clrbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7)); +} + +/** + * uart_branch_clk_enable_reg - enables branch clock + * + * Enables branch clock for GSBI UART port. + */ +static void uart_branch_clk_enable_reg(unsigned int gsbi_port) +{ + setbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(9)); +} + +/** + * uart_local_clock_enable - configures N value and enables root clocks + * + * Sets the N parameter of the divider and enables root clock and + * branch clocks for GSBI UART port. + */ +static void uart_local_clock_enable(unsigned int gsbi_port, unsigned int n, + unsigned int m) +{ + unsigned int reg_val, uart_ns_val; + void *const reg = (void *)GSBIn_UART_APPS_NS_REG(gsbi_port); + + /* + * Program the NS register, if applicable. NS registers are not + * set in the set_rate path because power can be saved by deferring + * the selection of a clocked source until the clock is enabled. + */ + reg_val = readl(reg); // REG(0x29D4+(0x20*((n)-1))) + reg_val &= ~(Uart_clk_ns_mask); + uart_ns_val = NS(BIT_POS_31,BIT_POS_16,n,m, 5, 4, 3, 1, 2, 0,3); + reg_val |= (uart_ns_val & Uart_clk_ns_mask); + writel(reg_val,reg); + + /* enable MNCNTR_EN */ + reg_val = readl(reg); + reg_val |= BIT(8); + writel(reg_val, reg); + + /* set source to PLL8 running @384MHz */ + reg_val = readl(reg); + reg_val |= 0x3; + writel(reg_val, reg); + + /* Enable root. */ + reg_val |= Uart_en_mask; + writel(reg_val, reg); + uart_branch_clk_enable_reg(gsbi_port); +} + +/** + * uart_set_gsbi_clk - enables HCLK for UART GSBI port + */ +static void uart_set_gsbi_clk(unsigned int gsbi_port) +{ + setbits_le32(GSBIn_HCLK_CTL_REG(gsbi_port), BIT(4)); +} + +/** + * uart_clock_config - configures UART clocks + * + * Configures GSBI UART dividers, enable root and branch clocks. + */ +void uart_clock_config(unsigned int gsbi_port, unsigned int m, + unsigned int n, unsigned int d, unsigned int clk_dummy) +{ + uart_set_rate_mnd(gsbi_port, m, d); + uart_pll_vote_clk_enable(clk_dummy); + uart_local_clock_enable(gsbi_port, n, m); + uart_set_gsbi_clk(gsbi_port); +} + +/** + * nand_clock_config - configure NAND controller clocks + * + * Enable clocks to EBI2. Must be invoked before touching EBI2 + * registers. + */ +void nand_clock_config(void) +{ + writel(CLK_BRANCH_ENA(1) | ALWAYS_ON_CLK_BRANCH_ENA(1), + EBI2_CLK_CTL_REG); + + /* Wait for clock to stabilize. */ + udelay(10); +} |