diff options
| author | Vikas Das <vdas@codeaurora.org> | 2014-09-22 17:49:56 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-15 21:56:56 +0200 |
| commit | 08f249e7d07e7742e202d08305822af2b3ddec78 (patch) | |
| tree | ad7403d9915d06d309e1a7227b3af62a00e71dae /src/soc/qualcomm/ipq806x/include | |
| parent | 239622677b3e3e20d1de8f79224edf1cc97d7083 (diff) | |
| download | coreboot-08f249e7d07e7742e202d08305822af2b3ddec78.tar.xz | |
ipq806x: Load TZBSP blob from coreboot ramstage
Read the TZBSP blob from CBFS and run it. A side effect of the blob
execution is switching the processor into User mode.
Starting TZBSP requires processor running in Supervisor mode, TZBSP
code is compiled for ARM. Coreboot is executing in System mode and is
compiled for Thumb. An assembler wrapper switches the execution mode
and interfaces between Thumb and ARM modes.
BUG=chrome-os-partner:34161
BRANCH=Storm
TEST=manual
With the preceeding patches the system successfully loads to
depthcharge in recovery mode.
Change-Id: I812b5cef95ba5562a005e005162d6391e502ecf8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7065cf3d17964a1d9038ec8906b469a08a79c6e2
Original-Change-Id: Ib14dbcbcbe489b595f4247d489d50f76a0e65948
Original-Signed-off-by: Varadarajan Narayanan <varada@qti.qualcomm.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/229026
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9690
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/ipq806x/include')
| -rw-r--r-- | src/soc/qualcomm/ipq806x/include/soc/memlayout.ld | 4 | ||||
| -rw-r--r-- | src/soc/qualcomm/ipq806x/include/soc/soc_services.h | 5 |
2 files changed, 7 insertions, 2 deletions
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld index 873f61cb1e..6a0d6ad815 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld @@ -54,9 +54,9 @@ SECTIONS DRAM_START(0x40000000) RAMSTAGE(0x40640000, 128K) - SYMBOL(memlayout_cbmem_top, 0x59FA0000) + SYMBOL(memlayout_cbmem_top, 0x59F80000) #ifndef __PRE_RAM__ - CBFS_CACHE(0x59FA0000, 256K) + CBFS_CACHE(0x59F80000, 384K) #endif DMA_COHERENT(0x5A000000, 2M) } diff --git a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h index 9e92bc71e3..b852d7f37e 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h +++ b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h @@ -27,4 +27,9 @@ extern u8 _memlayout_cbmem_top[]; /* Returns zero on success, nonzero on failure. */ int initialize_dram(void); +/* Loads and runs TZBSP, switches into user mode. */ +void start_tzbsp(void); + +int tz_init_wrapper(int, int, void *); + #endif |