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authorVadim Bendebury <vbendeb@chromium.org>2014-12-11 17:31:20 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-15 21:56:30 +0200
commit59b8c385986b8981cd9e34cbd04f45ecf42c1ed0 (patch)
tree237200174831d53112b9a78f33ece545ab92d5c6 /src/soc/qualcomm/ipq806x/include
parentfac642035e9bf1130b3caffd77dd1f5d9affdfdd (diff)
downloadcoreboot-59b8c385986b8981cd9e34cbd04f45ecf42c1ed0.tar.xz
storm: use different CBFS caches before and after DRAM is available
Booting depthcharge requires much larger CBFS cache, but by the time depthcharge is being booted DRAM is already initialized. Use different memory spaces for CBFS cache before and after DRAM is available. Also, make sure that CBMEM uses memory below CBFS cache in DRAM. BRANCH=storm BUG=chrome-os-partner:34161 TEST=with this change on Storm ramstage finds and boots depthcharge in recovery mode Change-Id: Icd1bbf4bcc5f9d92b2653b5a8891409105a25353 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e1e0b029b7fb09b84784373150cc4ce9eea7b3f5 Original-Change-Id: I33fd97806b2db6fab2adc44b67e5f54258642967 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234543 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9688 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/ipq806x/include')
-rw-r--r--src/soc/qualcomm/ipq806x/include/soc/memlayout.ld13
-rw-r--r--src/soc/qualcomm/ipq806x/include/soc/soc_services.h4
2 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index 7020f929c4..873f61cb1e 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -39,11 +39,24 @@ SECTIONS
QCA_SHARED_RAM(2A03F000, 4K)
*/
STACK(0x2A040000, 16K)
+#ifdef __PRE_RAM__
+ /*
+ * ipq8064 is different from most other ARM platforms: it loads the
+ * proprietary DRAM initialization code from CBFS (as opposed to compiling
+ * it in into rombase). As a result CBFS needs to be used before DRAM is
+ * availale, which means CBFS cache must be in SRAM, which in turn means
+ * that PRERAM_CBFS_CACHE description can not be used here.
+ */
CBFS_CACHE(0x2A044000, 96K)
+#endif
TTB(0x2A05C000, 16K)
SRAM_END(0x2A060000)
DRAM_START(0x40000000)
RAMSTAGE(0x40640000, 128K)
+ SYMBOL(memlayout_cbmem_top, 0x59FA0000)
+#ifndef __PRE_RAM__
+ CBFS_CACHE(0x59FA0000, 256K)
+#endif
DMA_COHERENT(0x5A000000, 2M)
}
diff --git a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h
index 8a936fe7d9..9e92bc71e3 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h
+++ b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h
@@ -20,6 +20,10 @@
#ifndef __SOC_QUALCOMM_IPQ806X_INCLUDE_SOC_SOC_SERVICES_H__
#define __SOC_QUALCOMM_IPQ806X_INCLUDE_SOC_SOC_SERVICES_H__
+#include <types.h>
+
+extern u8 _memlayout_cbmem_top[];
+
/* Returns zero on success, nonzero on failure. */
int initialize_dram(void);