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authorJulius Werner <jwerner@chromium.org>2015-02-19 14:51:15 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-21 08:22:28 +0200
commit2f37bd65518865688b9234afce0d467508d6f465 (patch)
treeeba5ed799de966299602b30c70d51dd40eaadd73 /src/soc/qualcomm/ipq806x/uart.c
parent1f60f971fc89ef841e81b978964b38278d597b1d (diff)
downloadcoreboot-2f37bd65518865688b9234afce0d467508d6f465.tar.xz
arm(64): Globally replace writel(v, a) with write32(a, v)
This patch is a raw application of the following spatch to src/: @@ expression A, V; @@ - writel(V, A) + write32(A, V) @@ expression A, V; @@ - writew(V, A) + write16(A, V) @@ expression A, V; @@ - writeb(V, A) + write8(A, V) @@ expression A; @@ - readl(A) + read32(A) @@ expression A; @@ - readb(A) + read8(A) BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6 Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254864 Reviewed-on: http://review.coreboot.org/9836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/ipq806x/uart.c')
-rw-r--r--src/soc/qualcomm/ipq806x/uart.c81
1 files changed, 40 insertions, 41 deletions
diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c
index ebe1913734..c9ef77014c 100644
--- a/src/soc/qualcomm/ipq806x/uart.c
+++ b/src/soc/qualcomm/ipq806x/uart.c
@@ -89,22 +89,22 @@ static const uart_params_t uart_board_param = {
static unsigned int msm_boot_uart_dm_init_rx_transfer(void *uart_dm_base)
{
/* Reset receiver */
- writel(MSM_BOOT_UART_DM_CMD_RESET_RX,
- MSM_BOOT_UART_DM_CR(uart_dm_base));
+ write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
+ MSM_BOOT_UART_DM_CMD_RESET_RX);
/* Enable receiver */
- writel(MSM_BOOT_UART_DM_CR_RX_ENABLE,
- MSM_BOOT_UART_DM_CR(uart_dm_base));
- writel(MSM_BOOT_UART_DM_DMRX_DEF_VALUE,
- MSM_BOOT_UART_DM_DMRX(uart_dm_base));
+ write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
+ MSM_BOOT_UART_DM_CR_RX_ENABLE);
+ write32(MSM_BOOT_UART_DM_DMRX(uart_dm_base),
+ MSM_BOOT_UART_DM_DMRX_DEF_VALUE);
/* Clear stale event */
- writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT,
- MSM_BOOT_UART_DM_CR(uart_dm_base));
+ write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
+ MSM_BOOT_UART_DM_CMD_RES_STALE_INT);
/* Enable stale event */
- writel(MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT,
- MSM_BOOT_UART_DM_CR(uart_dm_base));
+ write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
+ MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT);
return MSM_BOOT_UART_DM_E_SUCCESS;
}
@@ -200,17 +200,17 @@ void uart_tx_byte(int idx, unsigned char data)
void *base = uart_board_param.uart_dm_base;
/* Wait until transmit FIFO is empty. */
- while (!(readl(MSM_BOOT_UART_DM_SR(base)) &
+ while (!(read32(MSM_BOOT_UART_DM_SR(base)) &
MSM_BOOT_UART_DM_SR_TXEMT))
udelay(1);
/*
* TX FIFO is ready to accept new character(s). First write number of
* characters to be transmitted.
*/
- writel(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base));
+ write32(MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base), num_of_chars);
/* And now write the character(s) */
- writel(tx_data, MSM_BOOT_UART_DM_TF(base, 0));
+ write32(MSM_BOOT_UART_DM_TF(base, 0), tx_data);
}
#endif /* CONFIG_SERIAL_UART */
@@ -220,12 +220,12 @@ void uart_tx_byte(int idx, unsigned char data)
*/
static unsigned int msm_boot_uart_dm_reset(void *base)
{
- writel(MSM_BOOT_UART_DM_CMD_RESET_RX, MSM_BOOT_UART_DM_CR(base));
- writel(MSM_BOOT_UART_DM_CMD_RESET_TX, MSM_BOOT_UART_DM_CR(base));
- writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT,
- MSM_BOOT_UART_DM_CR(base));
- writel(MSM_BOOT_UART_DM_CMD_RES_TX_ERR, MSM_BOOT_UART_DM_CR(base));
- writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(base));
+ write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_RX);
+ write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_TX);
+ write32(MSM_BOOT_UART_DM_CR(base),
+ MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT);
+ write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_TX_ERR);
+ write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_STALE_INT);
return MSM_BOOT_UART_DM_E_SUCCESS;
}
@@ -238,40 +238,40 @@ static unsigned int msm_boot_uart_dm_init(void *uart_dm_base)
{
/* Configure UART mode registers MR1 and MR2 */
/* Hardware flow control isn't supported */
- writel(0x0, MSM_BOOT_UART_DM_MR1(uart_dm_base));
+ write32(MSM_BOOT_UART_DM_MR1(uart_dm_base), 0x0);
/* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */
- writel(MSM_BOOT_UART_DM_8_N_1_MODE,
- MSM_BOOT_UART_DM_MR2(uart_dm_base));
+ write32(MSM_BOOT_UART_DM_MR2(uart_dm_base),
+ MSM_BOOT_UART_DM_8_N_1_MODE);
/* Configure Interrupt Mask register IMR */
- writel(MSM_BOOT_UART_DM_IMR_ENABLED,
- MSM_BOOT_UART_DM_IMR(uart_dm_base));
+ write32(MSM_BOOT_UART_DM_IMR(uart_dm_base),
+ MSM_BOOT_UART_DM_IMR_ENABLED);
/*
* Configure Tx and Rx watermarks configuration registers
* TX watermark value is set to 0 - interrupt is generated when
* FIFO level is less than or equal to 0
*/
- writel(MSM_BOOT_UART_DM_TFW_VALUE,
- MSM_BOOT_UART_DM_TFWR(uart_dm_base));
+ write32(MSM_BOOT_UART_DM_TFWR(uart_dm_base),
+ MSM_BOOT_UART_DM_TFW_VALUE);
/* RX watermark value */
- writel(MSM_BOOT_UART_DM_RFW_VALUE,
- MSM_BOOT_UART_DM_RFWR(uart_dm_base));
+ write32(MSM_BOOT_UART_DM_RFWR(uart_dm_base),
+ MSM_BOOT_UART_DM_RFW_VALUE);
/* Configure Interrupt Programming Register */
/* Set initial Stale timeout value */
- writel(MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB,
- MSM_BOOT_UART_DM_IPR(uart_dm_base));
+ write32(MSM_BOOT_UART_DM_IPR(uart_dm_base),
+ MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB);
/* Configure IRDA if required */
/* Disabling IRDA mode */
- writel(0x0, MSM_BOOT_UART_DM_IRDA(uart_dm_base));
+ write32(MSM_BOOT_UART_DM_IRDA(uart_dm_base), 0x0);
/* Configure hunt character value in HCR register */
/* Keep it in reset state */
- writel(0x0, MSM_BOOT_UART_DM_HCR(uart_dm_base));
+ write32(MSM_BOOT_UART_DM_HCR(uart_dm_base), 0x0);
/*
* Configure Rx FIFO base address
@@ -286,11 +286,11 @@ static unsigned int msm_boot_uart_dm_init(void *uart_dm_base)
/* Enable/Disable Rx/Tx DM interfaces */
/* Data Mover not currently utilized. */
- writel(0x0, MSM_BOOT_UART_DM_DMEN(uart_dm_base));
+ write32(MSM_BOOT_UART_DM_DMEN(uart_dm_base), 0x0);
/* Enable transmitter */
- writel(MSM_BOOT_UART_DM_CR_TX_ENABLE,
- MSM_BOOT_UART_DM_CR(uart_dm_base));
+ write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
+ MSM_BOOT_UART_DM_CR_TX_ENABLE);
/* Initialize Receive Path */
msm_boot_uart_dm_init_rx_transfer(uart_dm_base);
@@ -311,7 +311,7 @@ void uart_init(int idx)
dm_base = uart_board_param.uart_dm_base;
- if (readl(MSM_BOOT_UART_DM_CSR(dm_base)) == UART_DM_CLK_RX_TX_BIT_RATE)
+ if (read32(MSM_BOOT_UART_DM_CSR(dm_base)) == UART_DM_CLK_RX_TX_BIT_RATE)
return; /* UART must have been already initialized. */
gsbi_base = uart_board_param.uart_gsbi_base;
@@ -325,10 +325,9 @@ void uart_init(int idx)
uart_board_param.mnd_value.d_value,
0);
- writel(GSBI_PROTOCOL_CODE_I2C_UART <<
- GSBI_CTRL_REG_PROTOCOL_CODE_S,
- GSBI_CTRL_REG(gsbi_base));
- writel(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(dm_base));
+ write32(GSBI_CTRL_REG(gsbi_base),
+ GSBI_PROTOCOL_CODE_I2C_UART << GSBI_CTRL_REG_PROTOCOL_CODE_S);
+ write32(MSM_BOOT_UART_DM_CSR(dm_base), UART_DM_CLK_RX_TX_BIT_RATE);
/* Intialize UART_DM */
msm_boot_uart_dm_init(dm_base);
@@ -355,7 +354,7 @@ void uart_tx_flush(int idx)
{
void *base = uart_board_param.uart_dm_base;
- while (!(readl(MSM_BOOT_UART_DM_SR(base)) &
+ while (!(read32(MSM_BOOT_UART_DM_SR(base)) &
MSM_BOOT_UART_DM_SR_TXEMT))
;
}