diff options
author | Julius Werner <jwerner@chromium.org> | 2015-02-19 14:51:15 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-21 08:22:28 +0200 |
commit | 2f37bd65518865688b9234afce0d467508d6f465 (patch) | |
tree | eba5ed799de966299602b30c70d51dd40eaadd73 /src/soc/qualcomm/ipq806x/usb.c | |
parent | 1f60f971fc89ef841e81b978964b38278d597b1d (diff) | |
download | coreboot-2f37bd65518865688b9234afce0d467508d6f465.tar.xz |
arm(64): Globally replace writel(v, a) with write32(a, v)
This patch is a raw application of the following spatch to src/:
@@
expression A, V;
@@
- writel(V, A)
+ write32(A, V)
@@
expression A, V;
@@
- writew(V, A)
+ write16(A, V)
@@
expression A, V;
@@
- writeb(V, A)
+ write8(A, V)
@@
expression A;
@@
- readl(A)
+ read32(A)
@@
expression A;
@@
- readb(A)
+ read8(A)
BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)
Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6
Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254864
Reviewed-on: http://review.coreboot.org/9836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/ipq806x/usb.c')
-rw-r--r-- | src/soc/qualcomm/ipq806x/usb.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/src/soc/qualcomm/ipq806x/usb.c b/src/soc/qualcomm/ipq806x/usb.c index 69b3998624..d7dac7243c 100644 --- a/src/soc/qualcomm/ipq806x/usb.c +++ b/src/soc/qualcomm/ipq806x/usb.c @@ -101,16 +101,16 @@ static struct usb_dwc3 * const usb_host2_dwc3 = (void *)USB_HOST2_DWC3_BASE; static void setup_dwc3(struct usb_dwc3 *dwc3) { - writel(0x1 << 31 | 0x1 << 25 | 0x1 << 24 | 0x1 << 19 | 0x1 << 18 | 0x1 << 1 | 0x1 << 0 | 0, - &dwc3->usb3pipectl); + write32(&dwc3->usb3pipectl, + 0x1 << 31 | 0x1 << 25 | 0x1 << 24 | 0x1 << 19 | 0x1 << 18 | 0x1 << 1 | 0x1 << 0 | 0); - writel(0x1 << 31 | 0x9 << 10 | 0x1 << 8 | 0x1 << 6 | 0, - &dwc3->usb2phycfg); + write32(&dwc3->usb2phycfg, + 0x1 << 31 | 0x9 << 10 | 0x1 << 8 | 0x1 << 6 | 0); - writel(0x2 << 19 | 0x1 << 16 | 0x1 << 12 | 0x1 << 11 | 0x1 << 10 | 0x1 << 2 | 0, - &dwc3->ctl); + write32(&dwc3->ctl, + 0x2 << 19 | 0x1 << 16 | 0x1 << 12 | 0x1 << 11 | 0x1 << 10 | 0x1 << 2 | 0); - writel(0x32 << 22 | 0x1 << 15 | 0x10 << 0 | 0, &dwc3->uctl); + write32(&dwc3->uctl, 0x32 << 22 | 0x1 << 15 | 0x10 << 0 | 0); udelay(5); @@ -121,16 +121,16 @@ static void setup_dwc3(struct usb_dwc3 *dwc3) static void setup_phy(struct usb_qc_phy *phy) { - writel(0x1 << 24 | 0x1 << 8 | 0x1 << 7 | 0x19 << 0 | 0, - &phy->ss_phy_ctrl); + write32(&phy->ss_phy_ctrl, + 0x1 << 24 | 0x1 << 8 | 0x1 << 7 | 0x19 << 0 | 0); - writel(0x1 << 26 | 0x1 << 25 | 0x1 << 24 | 0x1 << 21 | 0x1 << 20 | 0x1 << 18 | 0x1 << 17 | 0x1 << 11 | 0x1 << 9 | 0x1 << 8 | 0x1 << 7 | 0x7 << 4 | 0x1 << 1 | 0, - &phy->hs_phy_ctrl); + write32(&phy->hs_phy_ctrl, + 0x1 << 26 | 0x1 << 25 | 0x1 << 24 | 0x1 << 21 | 0x1 << 20 | 0x1 << 18 | 0x1 << 17 | 0x1 << 11 | 0x1 << 9 | 0x1 << 8 | 0x1 << 7 | 0x7 << 4 | 0x1 << 1 | 0); - writel(0x6e << 20 | 0x20 << 14 | 0x17 << 8 | 0x9 << 3 | 0, - &phy->ss_phy_param1); + write32(&phy->ss_phy_param1, + 0x6e << 20 | 0x20 << 14 | 0x17 << 8 | 0x9 << 3 | 0); - writel(0x1 << 2, &phy->general_cfg); /* set XHCI 1.00 compliance */ + write32(&phy->general_cfg, 0x1 << 2); /* set XHCI 1.00 compliance */ udelay(5); clrbits_le32(&phy->ss_phy_ctrl, 0x1 << 7); /* deassert SS PHY reset */ @@ -141,9 +141,9 @@ static void crport_handshake(void *capture_reg, void *acknowledge_bit, u32 data) int usec = 100; if (capture_reg) - writel(data, capture_reg); + write32(capture_reg, data); - writel(0x1 << 0, acknowledge_bit); + write32(acknowledge_bit, 0x1 << 0); while (read32(acknowledge_bit) && --usec) udelay(1); |