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| author | Vadim Bendebury <vbendeb@chromium.org> | 2014-04-09 19:23:54 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-12-05 20:22:55 +0100 |
| commit | db3e2f0931a52bee6e59d09df572fd0bfb481ff9 (patch) | |
| tree | 0742e81b5cd1675372b5b6897e9cc9fef7902a34 /src/soc/qualcomm/ipq806x | |
| parent | 63956e63ce6e9035aaf0a7f0363d064acb083816 (diff) | |
| download | coreboot-db3e2f0931a52bee6e59d09df572fd0bfb481ff9.tar.xz | |
ipq8064: Make clock code build in coreboot
Include clock.c in the appropriate coreboot stages, modify the code to
build cleanly. Use proper pointer cast in .h files.
BUG=chrome-os-partner:27784
TEST='emerge-storm coreboot' still succeeds
Original-Change-Id: I227c871b17e571f6a1db3ada3821dbb1ee884e59
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196407
(cherry picked from commit 75decceccd97298974891bb98b796eccfe11f46c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I7d44464d4ca8153e84407fc05a25e2e79e74901e
Reviewed-on: http://review.coreboot.org/7271
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Diffstat (limited to 'src/soc/qualcomm/ipq806x')
| -rw-r--r-- | src/soc/qualcomm/ipq806x/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/soc/qualcomm/ipq806x/clock.c | 7 | ||||
| -rw-r--r-- | src/soc/qualcomm/ipq806x/include/clock.h | 9 | ||||
| -rw-r--r-- | src/soc/qualcomm/ipq806x/include/iomap.h | 2 |
4 files changed, 11 insertions, 10 deletions
diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 904251102d..cffcc1223d 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -1,10 +1,13 @@ bootblock-y += cbfs.c +bootblock-y += clock.c bootblock-y += gpio.c romstage-y += cbfs.c +romstage-y += clock.c romstage-y += gpio.c ramstage-y += cbfs.c +ramstage-y += clock.c ramstage-y += gpio.c ramstage-y += timer.c diff --git a/src/soc/qualcomm/ipq806x/clock.c b/src/soc/qualcomm/ipq806x/clock.c index 882be02f9f..70afcec419 100644 --- a/src/soc/qualcomm/ipq806x/clock.c +++ b/src/soc/qualcomm/ipq806x/clock.c @@ -2,11 +2,8 @@ * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved. */ -#include <common.h> -#include <asm/arch-ipq806x/clock.h> -#include <asm/arch-ipq806x/nss/clock.h> -#include <asm/arch-ipq806x/iomap.h> -#include <asm/io.h> +#include <delay.h> +#include <clock.h> /** * uart_pll_vote_clk_enable - enables PLL8 diff --git a/src/soc/qualcomm/ipq806x/include/clock.h b/src/soc/qualcomm/ipq806x/include/clock.h index 263b81b0b8..c5d4121169 100644 --- a/src/soc/qualcomm/ipq806x/include/clock.h +++ b/src/soc/qualcomm/ipq806x/include/clock.h @@ -30,10 +30,11 @@ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __PLATFORM_IPQ860X_CLOCK_H_ -#define __PLATFORM_IPQ860X_CLOCK_H_ +#ifndef __IPQ860X_CLOCK_H_ +#define __IPQ860X_CLOCK_H_ + +#include <iomap.h> -#include <asm/io.h> /* UART clock @ 7.3728 MHz */ #define UART_DM_CLK_RX_TX_BIT_RATE 0xCC @@ -51,7 +52,7 @@ #define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1))) #define BB_PLL_ENA_SC0_REG REG(0x34C0) #define BB_PLL8_STATUS_REG REG(0x3158) -#define REG(off) (MSM_CLK_CTL_BASE + (off)) +#define REG(off) ((void *)(MSM_CLK_CTL_BASE + (off))) #define PLL8_STATUS_BIT 16 #define PLL_LOCK_DET_STATUS_REG REG(0x03420) diff --git a/src/soc/qualcomm/ipq806x/include/iomap.h b/src/soc/qualcomm/ipq806x/include/iomap.h index 8642410616..8a4155ce6b 100644 --- a/src/soc/qualcomm/ipq806x/include/iomap.h +++ b/src/soc/qualcomm/ipq806x/include/iomap.h @@ -52,7 +52,7 @@ #define MSM_GPT_BASE (MSM_TMR_BASE + 0x04) #define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) -#define GPT_REG(off) (((uint8_t *)(MSM_GPT_BASE)) + (off)) +#define GPT_REG(off) ((void *)(MSM_GPT_BASE + (off))) #define DGT_REG(off) (MSM_DGT_BASE + (off)) #define APCS_WDT0_EN (MSM_TMR_BASE + 0x0040) |