soc/qualcomm/qcs405: Support for new SoC

Adding the basic infrastruture soc support for qcs405 and
a new build variant.

TEST=build

Change-Id: Ia379cf375e4459ed55cc36cb8a0a92cab18b705e
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

2 files changed, 71 insertions, 0 deletions

diff --git a/src/soc/qualcomm/qcs405/include/soc/gpio.h b/src/soc/qualcomm/qcs405/include/soc/gpio.h
new file mode 100644
index 0000000000..e1ad453e4e
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/include/soc/gpio.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_QUALCOMM_QCS405_GPIO_H_
+#define _SOC_QUALCOMM_QCS405_GPIO_H_
+
+#include <types.h>
+
+typedef u32 gpio_t;
+
+#endif // _SOC_QUALCOMM_QCS405_GPIO_H_
diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld
new file mode 100644
index 0000000000..d6e4dfb361
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <memlayout.h>
+#include <arch/header.ld>
+
+/* SYSTEM_IMEM : 0x8600000 - 0x8607FFF */
+#define SSRAM_START(addr) SYMBOL(ssram, addr)
+#define SSRAM_END(addr) SYMBOL(essram, addr)
+
+/* BOOT_IMEM   : 0x8C00000 - 0x8D80000 */
+#define BSRAM_START(addr) SYMBOL(bsram, addr)
+#define BSRAM_END(addr) SYMBOL(ebsram, addr)
+
+SECTIONS
+{
+	SSRAM_START(0x8600000)
+	SSRAM_END(0x8608000)
+
+	BSRAM_START(0x8C00000)
+	OVERLAP_VERSTAGE_ROMSTAGE(0x8C00000, 100K)
+	REGION(fw_reserved2, 0x8C19000, 0x16000, 4096)
+	BOOTBLOCK(0x8C2F000, 40K)
+	TTB(0x8C39000, 56K)
+	VBOOT2_WORK(0x8C47000, 16K)
+	STACK(0x8C4B000, 16K)
+	TIMESTAMP(0x8C4F000, 1K)
+	PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K)
+	PRERAM_CBFS_CACHE(0x8C57400, 70K)
+	REGION(bsram_unused, 0x8C68C00, 0xA2400, 0x100)
+	BSRAM_END(0x8D80000)
+
+	DRAM_START(0x90000000)
+	POSTRAM_CBFS_CACHE(0x90000000, 384K)
+	RAMSTAGE(0x90800000, 128K)
+}