diff options
| author | Jacob Garber <jgarber1@ualberta.ca> | 2019-07-23 11:46:24 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-07-29 06:09:17 +0000 |
| commit | 53b4b2850c0db509c9d0d5da4d2975710f685bd7 (patch) | |
| tree | cbbe3501ec4a3af90c4d5031f54bb5e4f72454d6 /src/soc/qualcomm/qcs405 | |
| parent | 767c4b28998aff563c36e2f2000e4768b68add8f (diff) | |
| download | coreboot-53b4b2850c0db509c9d0d5da4d2975710f685bd7.tar.xz | |
soc/qualcomm/qcs405: Handle invalid QUP and BLSP
Print an error message and return if an invalid QUP or BLSP is
encountered. This prevents a possible null pointer dereference
of spi_clk.
Change-Id: I374e15ce899c651df9c2d3e0f1ec646e33d4bdb2
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1401086
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/qualcomm/qcs405')
| -rw-r--r-- | src/soc/qualcomm/qcs405/clock.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index de42147432..b7dd51b2a6 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -235,12 +235,16 @@ void clock_configure_spi(int blsp, int qup, uint32_t hz) spi_clk = (struct qcs405_clock *) &gcc->blsp1_qup4_spi_clk; break; + default: + printk(BIOS_ERR, "Invalid QUP %d\n", qup); + return; } - } else if (blsp == 2) + } else if (blsp == 2) { spi_clk = (struct qcs405_clock *)&gcc->blsp2_qup0_spi_clk; - - else - printk(BIOS_ERR, "BLSP%d not supported\n", blsp); + } else { + printk(BIOS_ERR, "BLSP %d not supported\n", blsp); + return; + } clock_configure(spi_clk, spi_cfg, hz, ARRAY_SIZE(spi_cfg)); } |