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author | T Michael Turney <mturney@codeaurora.org> | 2019-11-27 19:28:23 -0800 |
---|---|---|
committer | Julius Werner <jwerner@chromium.org> | 2020-04-21 21:53:08 +0000 |
commit | cea0d9c0ffc06359b01310c0dd728b4527c0013d (patch) | |
tree | 4bf61e0d7525efc8bad62fc14c7b73bfc6699a19 /src/soc/qualcomm/sc7180/Makefile.inc | |
parent | 9d25207aaf93cb8052910f11fc1febd7865fb6e9 (diff) | |
download | coreboot-cea0d9c0ffc06359b01310c0dd728b4527c0013d.tar.xz |
sc7180: Add QUPv3 FW load & config
UART driver requires firmware loading
Developer/Reviewer, be aware of this patch from Napali:
https://review.coreboot.org/c/coreboot/+/25372/78
https://review.coreboot.org/c/coreboot/+/27483/58
Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/qualcomm/sc7180/Makefile.inc')
-rw-r--r-- | src/soc/qualcomm/sc7180/Makefile.inc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 5f4dc1d756..554efd8801 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -10,6 +10,8 @@ bootblock-y += gpio.c bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c bootblock-y += clock.c bootblock-$(CONFIG_SC7180_QSPI) += qspi.c +bootblock-y += qupv3_config.c +bootblock-y += qcom_qup_se.c ################################################################################ verstage-y += timer.c @@ -43,6 +45,8 @@ ramstage-y += clock.c ramstage-$(CONFIG_SC7180_QSPI) += qspi.c ramstage-y += aop_load_reset.c ramstage-y += usb.c +ramstage-y += qupv3_config.c +ramstage-y += qcom_qup_se.c ################################################################################ |