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| author | Patrick Georgi <pgeorgi@google.com> | 2019-12-05 19:56:53 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-05 19:37:31 +0000 |
| commit | b9d5b264584affa666adaa0e364e99f86361fd16 (patch) | |
| tree | edd7ea897c2812c00bac24d32b80f65ab8c37950 /src/soc/qualcomm/sc7180/clock.c | |
| parent | 68b6eb78d2b86d43d3d285a88a686de20751cb81 (diff) | |
| download | coreboot-b9d5b264584affa666adaa0e364e99f86361fd16.tar.xz | |
soc/qualcomm/sc7180: Adapt to recent API changes
Definitions were moved so that now device/mmio.h needs to be included
instead of arch/mmio.h. Also, don't use le32 conversion.
This follows the activities of commit 55009af42 (Change all
clrsetbits_leXX() to clrsetbitsXX()) and commit 1c371572188 (mmio: Add
clrsetbitsXX() API in place of updateX()).
Change-Id: Ie3af0d4f0b3331fe5572fc56915952547b512db7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37534
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/sc7180/clock.c')
| -rw-r--r-- | src/soc/qualcomm/sc7180/clock.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index 97b7b280ca..9092a4e185 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -62,10 +62,10 @@ struct clock_config qspi_core_cfg[] = { static int clock_configure_gpll0(void) { - setbits_le32(&gcc->gpll0.user_ctl_u, 1 << SCALE_FREQ_SHFT); + setbits32(&gcc->gpll0.user_ctl_u, 1 << SCALE_FREQ_SHFT); /* Keep existing GPLL0 configuration, in RUN mode @600Mhz. */ - setbits_le32(&gcc->gpll0.user_ctl, + setbits32(&gcc->gpll0.user_ctl, 1 << CLK_CTL_GPLL_PLLOUT_EVEN_SHFT | 1 << CLK_CTL_GPLL_PLLOUT_MAIN_SHFT | 1 << CLK_CTL_GPLL_PLLOUT_ODD_SHFT); @@ -77,7 +77,7 @@ static int clock_configure_mnd(struct sc7180_clock *clk, uint32_t m, uint32_t n, uint32_t d_2) { struct sc7180_mnd_clock *mnd = (struct sc7180_mnd_clock *)clk; - setbits_le32(&clk->rcg_cfg, + setbits32(&clk->rcg_cfg, RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); write32(&mnd->m, m & CLK_CTL_RCG_MND_BMSK); @@ -111,7 +111,7 @@ static int clock_configure(struct sc7180_clock *clk, clk_cfg[idx].d_2); /* Commit config to RCG*/ - setbits_le32(&clk->rcg_cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + setbits32(&clk->rcg_cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); return 0; } @@ -125,7 +125,7 @@ static int clock_enable_vote(void *cbcr_addr, void *vote_addr, uint32_t vote_bit) { /* Set clock vote bit */ - setbits_le32(vote_addr, BIT(vote_bit)); + setbits32(vote_addr, BIT(vote_bit)); /* Ensure clock is enabled */ while (clock_is_off(cbcr_addr)) @@ -137,7 +137,7 @@ static int clock_enable_vote(void *cbcr_addr, void *vote_addr, static int clock_enable(void *cbcr_addr) { /* Set clock enable bit */ - setbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); + setbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); /* Ensure clock is enabled */ while (clock_is_off(cbcr_addr)) @@ -149,7 +149,7 @@ static int clock_enable(void *cbcr_addr) void clock_reset_aop(void) { /* Bring AOP out of RESET */ - clrbits_le32(&aoss->aoss_cc_apcs_misc, BIT(AOP_RESET_SHFT)); + clrbits32(&aoss->aoss_cc_apcs_misc, BIT(AOP_RESET_SHFT)); } void clock_configure_qspi(uint32_t hz) @@ -166,9 +166,9 @@ int clock_reset_bcr(void *bcr_addr, bool reset) struct sc7180_bcr *bcr = bcr_addr; if (reset) - setbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + setbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); else - clrbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + clrbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); return 0; } |