sc7180: Add USB support

This includes USB QUSB2,QMP Phy and Controller support
And libpayload support for USB

Change-Id: I0651fc28dc227efbeb23eeefe9b96a3b940ae995
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

3 files changed, 136 insertions, 0 deletions

diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h
index e3941899f6..60570f0dc0 100644
--- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h
+++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h
@@ -25,4 +25,16 @@
 #define TLMM_SOUTH_TILE_BASE		0x03D00000
 #define TLMM_WEST_TILE_BASE		0x03500000
 
+/*
+ * USB BASE ADDRESSES
+ */
+#define QFPROM_BASE			0x00780000
+#define QUSB_PRIM_PHY_BASE		0x088e3000
+#define QUSB_PRIM_PHY_DIG_BASE		0x088e3200
+#define QMP_PHY_QSERDES_COM_REG_BASE	0x088e9000
+#define QMP_PHY_QSERDES_TX_REG_BASE	0x088e9200
+#define QMP_PHY_QSERDES_RX_REG_BASE	0x088e9400
+#define QMP_PHY_PCS_REG_BASE		0x088e9c00
+#define USB_HOST_DWC3_BASE		0x0a60c100
+
 #endif /*  __SOC_QUALCOMM_SC7180_ADDRESS_MAP_H__ */
diff --git a/src/soc/qualcomm/sc7180/include/soc/efuse.h b/src/soc/qualcomm/sc7180/include/soc/efuse.h
new file mode 100644
index 0000000000..baaa97179b
--- /dev/null
+++ b/src/soc/qualcomm/sc7180/include/soc/efuse.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2019 Qualcomm Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_QUALCOMM_SC7180_EFUSE_ADDRESS_MAP_H__
+#define __SOC_QUALCOMM_SC7180_EFUSE_ADDRESS_MAP_H__
+
+/**
+ *  USB EFUSE registers
+ */
+struct qfprom_corr {
+	u8 rsvd[0x4258 - 0x0];
+	u32 qusb_hstx_trim_lsb;
+};
+check_member(qfprom_corr, qusb_hstx_trim_lsb, 0x4258);
+
+#endif /* __SOC_QUALCOMM_SC7180_EFUSE_ADDRESS_MAP_H__ */
diff --git a/src/soc/qualcomm/sc7180/include/soc/usb.h b/src/soc/qualcomm/sc7180/include/soc/usb.h
new file mode 100644
index 0000000000..3a8816a027
--- /dev/null
+++ b/src/soc/qualcomm/sc7180/include/soc/usb.h
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2019 Qualcomm Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <types.h>
+
+#ifndef _SC7180_USB_H_
+#define _SC7180_USB_H_
+
+/* QSCRATCH_GENERAL_CFG register bit offset */
+#define PIPE_UTMI_CLK_SEL			BIT(0)
+#define PIPE3_PHYSTATUS_SW			BIT(3)
+#define PIPE_UTMI_CLK_DIS			BIT(8)
+
+/* Global USB3 Control  Registers */
+#define DWC3_GUSB3PIPECTL_DELAYP1TRANS		BIT(18)
+#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX		BIT(27)
+#define DWC3_GCTL_PRTCAPDIR(n)			((n) << 12)
+#define DWC3_GCTL_PRTCAP_OTG			3
+#define DWC3_GCTL_PRTCAP_HOST			1
+
+/* Global USB2 PHY Configuration Register */
+#define DWC3_GUSB2PHYCFG_USBTRDTIM(n)		((n) << 10)
+#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK	DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
+#define DWC3_GUSB2PHYCFG_PHYIF(n)		((n) << 3)
+#define DWC3_GUSB2PHYCFG_PHYIF_MASK		DWC3_GUSB2PHYCFG_PHYIF(1)
+#define USBTRDTIM_UTMI_8_BIT			9
+#define UTMI_PHYIF_8_BIT			0
+
+#define DWC3_GCTL_SCALEDOWN(n)			((n) << 4)
+#define DWC3_GCTL_SCALEDOWN_MASK		DWC3_GCTL_SCALEDOWN(3)
+#define DWC3_GCTL_DISSCRAMBLE			(1 << 3)
+#define DWC3_GCTL_U2EXIT_LFPS			(1 << 2)
+#define DWC3_GCTL_DSBLCLKGTNG			(1 << 0)
+
+#define PORT_TUNE1_MASK				0xf0
+
+/* QUSB2PHY_PWR_CTRL1 register related bits */
+#define POWER_DOWN				BIT(0)
+
+/* DEBUG_CTRL2 register value to program VSTATUS MUX for PHY status */
+#define DEBUG_CTRL2_MUX_PLL_LOCK_STATUS		0x4
+
+/* STAT5 register bits */
+#define VSTATUS_PLL_LOCK_STATUS_MASK		BIT(0)
+
+/* QUSB PHY register values */
+#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO	0x03
+#define QUSB2PHY_PLL_CLOCK_INVERTERS		0x7c
+#define QUSB2PHY_PLL_CMODE			0x80
+#define QUSB2PHY_PLL_LOCK_DELAY			0x0a
+#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO		0x19
+#define QUSB2PHY_PLL_BIAS_CONTROL_1		0x40
+#define QUSB2PHY_PLL_BIAS_CONTROL_2		0x22
+#define QUSB2PHY_PWR_CTRL2			0x21
+#define QUSB2PHY_IMP_CTRL1			0x08
+#define QUSB2PHY_IMP_CTRL2			0x58
+#define QUSB2PHY_PORT_TUNE1			0xc5
+#define QUSB2PHY_PORT_TUNE2			0x29
+#define QUSB2PHY_PORT_TUNE3			0xca
+#define QUSB2PHY_PORT_TUNE4			0x04
+#define QUSB2PHY_PORT_TUNE5			0x03
+#define QUSB2PHY_CHG_CTRL2			0x30
+
+/* USB3PHY_PCIE_USB3_PCS_PCS_STATUS bit */
+#define USB3_PCS_PHYSTATUS		BIT(6)
+
+struct usb_board_data {
+	/* Register values going to override from the boardfile */
+	u32 pll_bias_control_2;
+	u32 imp_ctrl1;
+	u32 port_tune1;
+};
+
+struct qmp_phy_init_tbl {
+	u32 *address;
+	u32 val;
+};
+
+void setup_usb_host0(struct usb_board_data *data);
+
+/* Call reset_ before setup_ */
+void reset_usb0(void);
+
+
+#endif /* _SC7180_USB_H_ */