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| author | Nico Huber <nico.h@gmx.de> | 2020-09-13 21:59:14 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-09-14 20:15:06 +0000 |
| commit | 308540de807a4af57bdcde97c695f770ecc4a9ad (patch) | |
| tree | 472e920edb33f106c11500bacb0a63a13dd007f2 /src/soc/qualcomm/sc7180/qupv3_uart.c | |
| parent | 08e8e47d03bd181762ec2cfa81c4bfa155729337 (diff) | |
| download | coreboot-308540de807a4af57bdcde97c695f770ecc4a9ad.tar.xz | |
nb/intel/ironlake: Reserve gap betwen TSEG and BGSM
There may be a gap between TSEG and the graphics stolen memory due to
the alignment done in `raminit.c`. If we allocate MMIO resources in
this range, it misbehaves unpredictably, so reserve it.
TEST=Booted Thinkpad X201s, allocated resources are above TOLUD.
Change-Id: If305e9751ebf4edc945cf038ed72698f3696e52d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45325
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/sc7180/qupv3_uart.c')
0 files changed, 0 insertions, 0 deletions