diff options
| author | Taniya Das <tdas@codeaurora.org> | 2020-04-03 21:37:27 +0530 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2020-04-21 21:50:55 +0000 |
| commit | 9d25207aaf93cb8052910f11fc1febd7865fb6e9 (patch) | |
| tree | b861ddd676c64b5adb1c3cf5d08c0b86b7b9821e /src/soc/qualcomm/sc7180 | |
| parent | ef5ff0b49a5d61b8dfc313fdddba3f07e3f7a8fc (diff) | |
| download | coreboot-9d25207aaf93cb8052910f11fc1febd7865fb6e9.tar.xz | |
sc7180: clock: Define the UART frequency for QUPV3
The frequency to be used by UART client is 7.3728MHz, thus define it in
the clock header to be used by the driver.
Tested: UART frequency request by client driver.
Change-Id: I1ced350fe9826ea05b03ffc11aced2c21fe85c9e
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/qualcomm/sc7180')
| -rw-r--r-- | src/soc/qualcomm/sc7180/clock.c | 2 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7180/include/soc/clock.h | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index b6b6d46061..56185eec8a 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -22,7 +22,7 @@ struct clock_config qup_cfg[] = { { - .hz = 7372800, + .hz = QUPV3_UART_SRC_HZ, .src = SRC_GPLL0_EVEN_300MHZ, .div = DIV(1), .m = 384, diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h index 2a8af28858..25903fb42c 100644 --- a/src/soc/qualcomm/sc7180/include/soc/clock.h +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -32,6 +32,7 @@ #define SRC_XO_HZ (19200 * KHz) #define GPLL0_EVEN_HZ (300 * MHz) #define GPLL0_MAIN_HZ (600 * MHz) +#define QUPV3_UART_SRC_HZ 7372800 #define SRC_XO_19_2MHZ 0 #define SRC_GPLL0_MAIN_600MHZ 1 |