sdm845: Add USB support on cheza platform

This patch adds code to initialize two USB DWC3.0 controllers
and its associated QUSB V2 10nm PHYs to the SDM845 SOC, and uses them to
initialize USB3.0 on the cheza mainboard.

Synopsis controller initialization and configuration sequences taken from
USB 3.0 HPG chapter 2.2 and refer PHY HPG chapter 10.2 for QUSB phy
programming.

Includes Super speed mode support.

TEST=USB keypad and mass-storage device enumeration tested with this patch

Change-Id: I475a7757239acb8ef22a4d61afd59b304a7f0acc
Signed-off-by: Chandana Kishori Chiluveru <cchiluve@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

4 files changed, 172 insertions, 6 deletions

diff --git a/src/soc/qualcomm/sdm845/include/soc/addressmap.h b/src/soc/qualcomm/sdm845/include/soc/addressmap.h
index 5a94e23e96..bf4b30b32b 100644
--- a/src/soc/qualcomm/sdm845/include/soc/addressmap.h
+++ b/src/soc/qualcomm/sdm845/include/soc/addressmap.h
@@ -25,4 +25,23 @@
 #define GCC_BASE			0x00100000
 #define AOSS_CC_BASE			0x0C2F0000
 
+/*
+ * USB BASE ADDRESSES
+ */
+#define QFPROM_BASE			0x00780000
+#define QUSB_PRIM_PHY_BASE		0x088e2000
+#define QUSB_PRIM_PHY_DIG_BASE		0x088e2200
+#define QUSB_SEC_PHY_BASE		0x088e3000
+#define QUSB_SEC_PHY_DIG_BASE		0x088e3200
+#define QMP_PHY_QSERDES_COM_REG_BASE	0x088e9000
+#define QMP_PHY_QSERDES_TX_REG_BASE	0x088e9200
+#define QMP_PHY_QSERDES_RX_REG_BASE	0x088e9400
+#define QMP_PHY_PCS_REG_BASE		0x088e9c00
+#define QMP_UNIPHY_QSERDES_COM_REG_BASE	0x088eb000
+#define QMP_UNIPHY_QSERDES_TX_REG_BASE	0x088eb200
+#define QMP_UNIPHY_QSERDES_RX_REG_BASE	0x088eb400
+#define QMP_UNIPHY_PCS_REG_BASE		0x088eb800
+#define USB_HOST0_DWC3_BASE		0x0a60c100
+#define USB_HOST1_DWC3_BASE		0x0a80c100
+
 #endif /*  __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__ */
diff --git a/src/soc/qualcomm/sdm845/include/soc/clock.h b/src/soc/qualcomm/sdm845/include/soc/clock.h
index 9f0533f33f..6aee9c14f3 100644
--- a/src/soc/qualcomm/sdm845/include/soc/clock.h
+++ b/src/soc/qualcomm/sdm845/include/soc/clock.h
@@ -74,7 +74,14 @@ struct sdm845_gpll {
 
 struct sdm845_gcc {
 	struct sdm845_gpll gpll0;
-	u8 _res0[0x17000 - 0x1000];
+	u8 _res0[0xf000 - 0x1000];
+	u32 usb30_prim_bcr;
+	u8 _res1[0x10000 - 0xf004];
+	u32 usb30_sec_bcr;
+	u8 _res2[0x12000 - 0x10004];
+	u32 qusb2phy_prim_bcr;
+	u32 qusb2phy_sec_bcr;
+	u8 _res3[0x17000 - 0x12008];
 	u32 qup_wrap0_bcr;
 	u32 qup_wrap0_m_ahb_cbcr;
 	u32 qup_wrap0_s_ahb_cbcr;
@@ -82,9 +89,9 @@ struct sdm845_gcc {
 	u32 qup_wrap0_core_cdivr;
 	u32 qup_wrap0_core_2x_cbcr;
 	struct sdm845_rcg qup_wrap0_core_2x;
-	u8 _res1[0x17030 - 0x17020];
+	u8 _res4[0x17030 - 0x17020];
 	struct sdm845_qupv3_clock qup_wrap0_s[8];
-	u8 _res2[0x18000 - 0x179b0];
+	u8 _res5[0x18000 - 0x179b0];
 	u32 qup_wrap1_bcr;
 	u32 qup_wrap1_core_2x_cbcr;
 	u32 qup_wrap1_core_cbcr;
@@ -92,14 +99,28 @@ struct sdm845_gcc {
 	u32 qup_wrap1_s_ahb_cbcr;
 	struct sdm845_qupv3_clock qup_wrap1_s[8];
 	u32 qup_wrap1_core_cdivr;
-	u8 _res4[0x4B000 - 0x18998];
+	u8 _res6[0x4B000 - 0x18998];
 	u32 qspi_cnoc_ahb_cbcr;
 	u32 qspi_core_cbcr;
 	struct sdm845_rcg qspi_core;
-	u8 _res5[0x5200c-0x4b010];
+	u8 _res7[0x50000-0x4b010];
+	u32 usb3_phy_prim_bcr;
+	u32 usb3phy_phy_prim_bcr;
+	u32 usb3_dp_phy_prim_bcr;
+	u32 usb3_phy_sec_bcr;
+	u32 usb3phy_phy_sec_bcr;
+	u8 _res8[0x5200c-0x50014];
 	u32 apcs_clk_br_en1;
-	u8 _res6[0x1000000-0x52010];
+	u8 _res9[0x1000000-0x52010];
 };
+check_member(sdm845_gcc, usb30_prim_bcr, 0xf000);
+check_member(sdm845_gcc, usb30_sec_bcr, 0x10000);
+check_member(sdm845_gcc, qusb2phy_prim_bcr, 0x12000);
+check_member(sdm845_gcc, qusb2phy_sec_bcr, 0x12004);
+check_member(sdm845_gcc, usb3phy_phy_prim_bcr, 0x50004);
+check_member(sdm845_gcc, usb3_phy_prim_bcr, 0x50000);
+check_member(sdm845_gcc, usb3_phy_sec_bcr, 0x5000c);
+check_member(sdm845_gcc, usb3phy_phy_sec_bcr, 0x50010);
 check_member(sdm845_gcc, apcs_clk_br_en1, 0x5200c);
 
 struct sdm845_aoss {
diff --git a/src/soc/qualcomm/sdm845/include/soc/efuse.h b/src/soc/qualcomm/sdm845/include/soc/efuse.h
new file mode 100644
index 0000000000..309193cf43
--- /dev/null
+++ b/src/soc/qualcomm/sdm845/include/soc/efuse.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2018 Qualcomm Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_QUALCOMM_SDM845_EFUSE_ADDRESS_MAP_H__
+#define __SOC_QUALCOMM_SDM845_EFUSE_ADDRESS_MAP_H__
+
+/**
+ *  USB EFUSE registers
+ */
+struct qfprom_corr {
+	u8 rsvd[0x41E8 - 0x0];
+	u32 qusb_hstx_trim_lsb;
+	u32 qusb_hstx_trim_msb;
+};
+
+check_member(qfprom_corr, qusb_hstx_trim_lsb, 0x41E8);
+check_member(qfprom_corr, qusb_hstx_trim_msb, 0x41EC);
+#endif /* __SOC_QUALCOMM_SDM845_EFUSE_ADDRESS_MAP_H__ */
diff --git a/src/soc/qualcomm/sdm845/include/soc/usb.h b/src/soc/qualcomm/sdm845/include/soc/usb.h
new file mode 100644
index 0000000000..b657676763
--- /dev/null
+++ b/src/soc/qualcomm/sdm845/include/soc/usb.h
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2018 Qualcomm Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <types.h>
+
+#ifndef _SDM845_USB_H_
+#define _SDM845_USB_H_
+
+/* QSCRATCH_GENERAL_CFG register bit offset */
+#define PIPE_UTMI_CLK_SEL			BIT(0)
+#define PIPE3_PHYSTATUS_SW			BIT(3)
+#define PIPE_UTMI_CLK_DIS			BIT(8)
+
+/* Global USB3 Control  Registers */
+#define DWC3_GUSB3PIPECTL_DELAYP1TRANS		BIT(18)
+#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX		BIT(27)
+#define DWC3_GCTL_PRTCAPDIR(n)			((n) << 12)
+#define DWC3_GCTL_PRTCAP_OTG			3
+#define DWC3_GCTL_PRTCAP_HOST			1
+
+/* Global USB2 PHY Configuration Register */
+#define DWC3_GUSB2PHYCFG_USBTRDTIM(n)		((n) << 10)
+#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK	DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
+#define DWC3_GUSB2PHYCFG_PHYIF(n)		((n) << 3)
+#define DWC3_GUSB2PHYCFG_PHYIF_MASK		DWC3_GUSB2PHYCFG_PHYIF(1)
+#define USBTRDTIM_UTMI_8_BIT			9
+#define UTMI_PHYIF_8_BIT			0
+
+#define DWC3_GCTL_SCALEDOWN(n)			((n) << 4)
+#define DWC3_GCTL_SCALEDOWN_MASK		DWC3_GCTL_SCALEDOWN(3)
+#define DWC3_GCTL_DISSCRAMBLE			(1 << 3)
+#define DWC3_GCTL_U2EXIT_LFPS			(1 << 2)
+#define DWC3_GCTL_DSBLCLKGTNG			(1 << 0)
+
+#define PORT_TUNE1_MASK				0xf0
+
+/* QUSB2PHY_PWR_CTRL1 register related bits */
+#define POWER_DOWN				BIT(0)
+
+/* DEBUG_CTRL2 register value to program VSTATUS MUX for PHY status */
+#define DEBUG_CTRL2_MUX_PLL_LOCK_STATUS		0x4
+
+/* STAT5 register bits */
+#define VSTATUS_PLL_LOCK_STATUS_MASK		BIT(0)
+
+/* QUSB PHY register values */
+#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO	0x03
+#define QUSB2PHY_PLL_CLOCK_INVERTERS		0x7c
+#define QUSB2PHY_PLL_CMODE			0x80
+#define QUSB2PHY_PLL_LOCK_DELAY			0x0a
+#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO		0x19
+#define QUSB2PHY_PLL_BIAS_CONTROL_1		0x40
+#define QUSB2PHY_PLL_BIAS_CONTROL_2		0x20
+#define QUSB2PHY_PWR_CTRL2			0x21
+#define QUSB2PHY_IMP_CTRL1			0x0
+#define QUSB2PHY_IMP_CTRL2			0x58
+#define QUSB2PHY_PORT_TUNE1			0x30
+#define QUSB2PHY_PORT_TUNE2			0x29
+#define QUSB2PHY_PORT_TUNE3			0xca
+#define QUSB2PHY_PORT_TUNE4			0x04
+#define QUSB2PHY_PORT_TUNE5			0x03
+#define QUSB2PHY_CHG_CTRL2			0x0
+
+/* USB3PHY_PCIE_USB3_PCS_PCS_STATUS bit */
+#define USB3_PCS_PHYSTATUS		BIT(6)
+
+struct usb_board_data {
+	/* Register values going to override from the boardfile */
+	u32 pll_bias_control_2;
+	u32 imp_ctrl1;
+	u32 port_tune1;
+};
+
+struct qmp_phy_init_tbl {
+	u32 *address;
+	u32 val;
+};
+
+void setup_usb_host0(struct usb_board_data *data);
+void setup_usb_host1(struct usb_board_data *data);
+/* Call reset_ before setup_ */
+void reset_usb0(void);
+void reset_usb1(void);
+
+#endif /* _SDM845_USB_H_ */