diff options
| author | Mukesh Savaliya <msavaliy@codeaurora.org> | 2018-05-11 07:41:33 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-05 14:09:59 +0000 |
| commit | b02452b490321d27a014c8a3421a474fc6689a92 (patch) | |
| tree | 691177cbe9c4dce730e01d95253dc370ad953278 /src/soc/qualcomm/sdm845/mmu.c | |
| parent | 03f05cff2f9441cb20e78158e32160ec2e833350 (diff) | |
| download | coreboot-b02452b490321d27a014c8a3421a474fc6689a92.tar.xz | |
sdm845: Add SPI-NOR flash driver
TEST=build & run
Change-Id: Ie404faf37617d2ad792310709ca2063f9a372076
Signed-off-by: Mukesh Savaliya <msavaliy@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/25392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/qualcomm/sdm845/mmu.c')
| -rw-r--r-- | src/soc/qualcomm/sdm845/mmu.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/src/soc/qualcomm/sdm845/mmu.c b/src/soc/qualcomm/sdm845/mmu.c index 12219e8817..52e7733fa5 100644 --- a/src/soc/qualcomm/sdm845/mmu.c +++ b/src/soc/qualcomm/sdm845/mmu.c @@ -19,14 +19,19 @@ #include <soc/mmu.h> #include <soc/symbols.h> -void sdm845_mmu_init() +#define CACHED_RAM (MA_MEM | MA_S | MA_RW) +#define UNCACHED_RAM (MA_MEM | MA_S | MA_RW | MA_MEM_NC) +#define DEV_MEM (MA_DEV | MA_S | MA_RW) + +void sdm845_mmu_init(void) { mmu_init(); - mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), - MA_DEV | MA_S | MA_RW); - mmu_config_range((void *)_ssram, _ssram_size, MA_MEM | MA_S | MA_RW); - mmu_config_range((void *)_bsram, _bsram_size, MA_MEM | MA_S | MA_RW); + mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM); + mmu_config_range((void *)_ssram, _ssram_size, CACHED_RAM); + mmu_config_range((void *)_bsram, _bsram_size, CACHED_RAM); + mmu_config_range((void *)_dma_coherent, _dma_coherent_size, + UNCACHED_RAM); mmu_enable(); } |