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authorT Michael Turney <mturney@codeaurora.org>2020-03-06 10:46:23 -0800
committerJulius Werner <jwerner@chromium.org>2020-05-11 23:59:50 +0000
commit593a4c32dfc0d91d04596d9a85ddad36c28117e1 (patch)
tree0516c3fbae2859c79a721cad2faf275c10e629c8 /src/soc/qualcomm
parent16eb4031c69c694d991424ef0905cce1103050e8 (diff)
downloadcoreboot-593a4c32dfc0d91d04596d9a85ddad36c28117e1.tar.xz
sc7180: Adjust memory allocations per upstream comments
Update memory regions, etc. Change-Id: If852fe4465fb431809570be6cdccff3ad9d9f4f0 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39362 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm')
-rw-r--r--src/soc/qualcomm/sc7180/include/soc/memlayout.ld5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld
index fc796c1ff1..2a0cd8a417 100644
--- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld
@@ -27,6 +27,7 @@ SECTIONS
SSRAM_END(0x146AE000)
BSRAM_START(0x14800000)
+ REGION(pbl_timestamps, 0x14800000, 84K, 4K)
BOOTBLOCK(0x14815000, 40K)
PRERAM_CBFS_CACHE(0x1481F000, 70K)
PRERAM_CBMEM_CONSOLE(0x14830800, 32K)
@@ -48,8 +49,8 @@ SECTIONS
DRAM_START(0x80000000)
/* Various hardware/software subsystems make use of this area */
REGION(dram_aop, 0x80800000, 0x040000, 0x1000)
- REGION(dram_soc, 0x80900000, 0x300000, 0x1000)
- BL31(0x80C00000, 0x1A800000)
+ REGION(dram_soc, 0x80900000, 0x200000, 0x1000)
+ BL31(0x80B00000, 1M)
POSTRAM_CBFS_CACHE(0x9F800000, 16M)
RAMSTAGE(0xA0800000, 16M)
}