arm(64): Globally replace writel(v, a) with write32(a, v)

This patch is a raw application of the following spatch to src/:

@@
expression A, V;
@@
- writel(V, A)
+ write32(A, V)
@@
expression A, V;
@@
- writew(V, A)
+ write16(A, V)
@@
expression A, V;
@@
- writeb(V, A)
+ write8(A, V)
@@
expression A;
@@
- readl(A)
+ read32(A)
@@
expression A;
@@
- readb(A)
+ read8(A)

BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)

Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6
Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254864
Reviewed-on: http://review.coreboot.org/9836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

9 files changed, 159 insertions, 160 deletions

diff --git a/src/soc/qualcomm/ipq806x/blobs_init.c b/src/soc/qualcomm/ipq806x/blobs_init.c
index a3c0cfa28e..d513d2545a 100644
--- a/src/soc/qualcomm/ipq806x/blobs_init.c
+++ b/src/soc/qualcomm/ipq806x/blobs_init.c
@@ -107,7 +107,7 @@ void start_rpm(void)
 	u32 ready_mask = 1 << 10;
 	struct stopwatch sw;
 
-	if (readl(RPM_SIGNAL_COOKIE) == RPM_FW_MAGIC_NUM) {
+	if (read32(RPM_SIGNAL_COOKIE) == RPM_FW_MAGIC_NUM) {
 		printk(BIOS_INFO, "RPM appears to have already started\n");
 		return;
 	}
@@ -119,20 +119,20 @@ void start_rpm(void)
 	printk(BIOS_INFO, "Starting RPM\n");
 
 	/* Clear 'ready' indication. */
-	writel(readl(RPM_INT_ACK) & ~ready_mask, RPM_INT_ACK);
+	write32(RPM_INT_ACK, read32(RPM_INT_ACK) & ~ready_mask);
 
 	/* Set RPM entry address */
-	writel(load_addr, RPM_SIGNAL_ENTRY);
+	write32(RPM_SIGNAL_ENTRY, load_addr);
 	/* Set cookie */
-	writel(RPM_FW_MAGIC_NUM, RPM_SIGNAL_COOKIE);
+	write32(RPM_SIGNAL_COOKIE, RPM_FW_MAGIC_NUM);
 
 	/* Wait for RPM start indication, up to 100ms. */
 	stopwatch_init_usecs_expire(&sw, 100000);
-	while (!(readl(RPM_INT) & ready_mask))
+	while (!(read32(RPM_INT) & ready_mask))
 		if (stopwatch_expired(&sw))
 			die("RPM Initialization failed\n");
 
 	/* Acknowledge RPM initialization */
-	writel(ready_mask, RPM_INT_ACK);
+	write32(RPM_INT_ACK, ready_mask);
 }
 #endif  /* !__PRE_RAM__ */
diff --git a/src/soc/qualcomm/ipq806x/clock.c b/src/soc/qualcomm/ipq806x/clock.c
index 0b770da94f..0ffd83f032 100644
--- a/src/soc/qualcomm/ipq806x/clock.c
+++ b/src/soc/qualcomm/ipq806x/clock.c
@@ -14,7 +14,7 @@ void uart_pll_vote_clk_enable(unsigned int clk_dummy)
 	setbits_le32(BB_PLL_ENA_SC0_REG, BIT(8));
 
 	if (!clk_dummy)
-		while((readl(PLL_LOCK_DET_STATUS_REG) & BIT(8)) == 0);
+		while((read32(PLL_LOCK_DET_STATUS_REG) & BIT(8)) == 0);
 }
 
 /**
@@ -29,7 +29,7 @@ static void uart_set_rate_mnd(unsigned int gsbi_port, unsigned int m,
 	/* Assert MND reset. */
 	setbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7));
 	/* Program M and D values. */
-	writel(MD16(m, n), GSBIn_UART_APPS_MD_REG(gsbi_port));
+	write32(GSBIn_UART_APPS_MD_REG(gsbi_port), MD16(m, n));
 	/* Deassert MND reset. */
 	clrbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7));
 }
@@ -61,25 +61,25 @@ static void uart_local_clock_enable(unsigned int gsbi_port, unsigned int n,
 	* set in the set_rate path because power can be saved by deferring
 	* the selection of a clocked source until the clock is enabled.
 	*/
-	reg_val = readl(reg); // REG(0x29D4+(0x20*((n)-1)))
+	reg_val = read32(reg); // REG(0x29D4+(0x20*((n)-1)))
 	reg_val &= ~(Uart_clk_ns_mask);
 	uart_ns_val =  NS(BIT_POS_31,BIT_POS_16,n,m, 5, 4, 3, 1, 2, 0,3);
 	reg_val |= (uart_ns_val & Uart_clk_ns_mask);
-	writel(reg_val,reg);
+	write32(reg, reg_val);
 
 	/* enable MNCNTR_EN */
-	reg_val = readl(reg);
+	reg_val = read32(reg);
 	reg_val |= BIT(8);
-	writel(reg_val, reg);
+	write32(reg, reg_val);
 
 	/* set source to PLL8 running @384MHz */
-	reg_val = readl(reg);
+	reg_val = read32(reg);
 	reg_val |= 0x3;
-	writel(reg_val, reg);
+	write32(reg, reg_val);
 
 	/* Enable root. */
 	reg_val |= Uart_en_mask;
-	writel(reg_val, reg);
+	write32(reg, reg_val);
 	uart_branch_clk_enable_reg(gsbi_port);
 }
 
@@ -113,8 +113,8 @@ void uart_clock_config(unsigned int gsbi_port, unsigned int m,
  */
 void nand_clock_config(void)
 {
-	writel(CLK_BRANCH_ENA(1) | ALWAYS_ON_CLK_BRANCH_ENA(1),
-	       EBI2_CLK_CTL_REG);
+	write32(EBI2_CLK_CTL_REG,
+		CLK_BRANCH_ENA(1) | ALWAYS_ON_CLK_BRANCH_ENA(1));
 
 	/* Wait for clock to stabilize. */
 	udelay(10);
@@ -126,17 +126,17 @@ void nand_clock_config(void)
 void usb_clock_config(void)
 {
 	/* Magic clock initialization numbers, nobody knows how they work... */
-	writel(0x10, USB30_MASTER_CLK_CTL_REG);
-	writel(0x10, USB30_1_MASTER_CLK_CTL_REG);
-	writel(0x500DF, USB30_MASTER_CLK_MD);
-	writel(0xE40942, USB30_MASTER_CLK_NS);
-	writel(0x100D7, USB30_MOC_UTMI_CLK_MD);
-	writel(0xD80942, USB30_MOC_UTMI_CLK_NS);
-	writel(0x10, USB30_MOC_UTMI_CLK_CTL);
-	writel(0x10, USB30_1_MOC_UTMI_CLK_CTL);
-
-	writel(1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0 | 0,
-	       USB30_RESET);
+	write32(USB30_MASTER_CLK_CTL_REG, 0x10);
+	write32(USB30_1_MASTER_CLK_CTL_REG, 0x10);
+	write32(USB30_MASTER_CLK_MD, 0x500DF);
+	write32(USB30_MASTER_CLK_NS, 0xE40942);
+	write32(USB30_MOC_UTMI_CLK_MD, 0x100D7);
+	write32(USB30_MOC_UTMI_CLK_NS, 0xD80942);
+	write32(USB30_MOC_UTMI_CLK_CTL, 0x10);
+	write32(USB30_1_MOC_UTMI_CLK_CTL, 0x10);
+
+	write32(USB30_RESET,
+		1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0 | 0);
 	udelay(5);
-	writel(0, USB30_RESET);	/* deassert all USB resets again */
+	write32(USB30_RESET, 0);	/* deassert all USB resets again */
 }
diff --git a/src/soc/qualcomm/ipq806x/gpio.c b/src/soc/qualcomm/ipq806x/gpio.c
index a0a3df9495..c40b521101 100644
--- a/src/soc/qualcomm/ipq806x/gpio.c
+++ b/src/soc/qualcomm/ipq806x/gpio.c
@@ -73,7 +73,7 @@ void gpio_tlmm_config_set(gpio_t gpio, unsigned func,
         val |= (drvstr & GPIO_CFG_DRV_MASK) << GPIO_CFG_DRV_SHIFT;
         val |= (enable & GPIO_CFG_OE_MASK) << GPIO_CFG_OE_SHIFT;
 
-        writel(val, GPIO_CONFIG_ADDR(gpio));
+        write32(GPIO_CONFIG_ADDR(gpio), val);
 }
 
 /*******************************************************
@@ -99,7 +99,7 @@ void gpio_tlmm_config_get(gpio_t gpio, unsigned *func,
 	if (gpio_not_valid(gpio))
 		return;
 
-	val = readl(addr);
+	val = read32(addr);
 
 	*pull = (val >> GPIO_CFG_PULL_SHIFT) & GPIO_CFG_PULL_MASK;
 	*func = (val >> GPIO_CFG_FUNC_SHIFT) & GPIO_CFG_FUNC_MASK;
@@ -122,7 +122,7 @@ int gpio_get(gpio_t gpio)
 		return -1;
 
 
-	return (readl(GPIO_IN_OUT_ADDR(gpio)) >> GPIO_IO_IN_SHIFT) &
+	return (read32(GPIO_IN_OUT_ADDR(gpio)) >> GPIO_IO_IN_SHIFT) &
 		GPIO_IO_IN_MASK;
 }
 
@@ -131,7 +131,7 @@ void gpio_set(gpio_t gpio, int value)
 	if (gpio_not_valid(gpio))
 		return;
 
-	writel((value & 1) << GPIO_IO_OUT_SHIFT, GPIO_IN_OUT_ADDR(gpio));
+	write32(GPIO_IN_OUT_ADDR(gpio), (value & 1) << GPIO_IO_OUT_SHIFT);
 }
 
 void gpio_input_pulldown(gpio_t gpio)
diff --git a/src/soc/qualcomm/ipq806x/gsbi.c b/src/soc/qualcomm/ipq806x/gsbi.c
index 54adbe8db7..93270958a9 100644
--- a/src/soc/qualcomm/ipq806x/gsbi.c
+++ b/src/soc/qualcomm/ipq806x/gsbi.c
@@ -68,18 +68,18 @@ gsbi_return_t gsbi_init(gsbi_id_t gsbi_id, gsbi_protocol_t protocol)
 	if (!gsbi_ctl)
 		return GSBI_ID_ERROR;
 
-	writel((1 << GSBI_HCLK_CTL_GATE_ENA) | (1 << GSBI_HCLK_CTL_BRANCH_ENA),
-		GSBI_HCLK_CTL(gsbi_id));
+	write32(GSBI_HCLK_CTL(gsbi_id),
+		(1 << GSBI_HCLK_CTL_GATE_ENA) | (1 << GSBI_HCLK_CTL_BRANCH_ENA));
 
 	if (gsbi_init_board(gsbi_id))
 		return GSBI_UNSUPPORTED;
 
-	writel(0, GSBI_QUP_APSS_NS_REG(gsbi_id));
-	writel(0, GSBI_QUP_APSS_MD_REG(gsbi_id));
+	write32(GSBI_QUP_APSS_NS_REG(gsbi_id), 0);
+	write32(GSBI_QUP_APSS_MD_REG(gsbi_id), 0);
 
 	reg_val = ((m & GSBI_QUP_APPS_M_MASK) << GSBI_QUP_APPS_M_SHFT) |
 		  ((~n & GSBI_QUP_APPS_D_MASK) << GSBI_QUP_APPS_D_SHFT);
-	writel(reg_val, GSBI_QUP_APSS_MD_REG(gsbi_id));
+	write32(GSBI_QUP_APSS_MD_REG(gsbi_id), reg_val);
 
 	reg_val = (((~(n - m)) & GSBI_QUP_APPS_N_MASK) <<
 					GSBI_QUP_APPS_N_SHFT) |
@@ -88,18 +88,18 @@ gsbi_return_t gsbi_init(gsbi_id_t gsbi_id, gsbi_protocol_t protocol)
 		  (((pre_div - 1) & GSBI_QUP_APPS_PRE_DIV_MSK) <<
 				 GSBI_QUP_APPS_PRE_DIV_SFT) |
 		  (src & GSBI_QUP_APPS_SRC_SEL_MSK);
-	writel(reg_val, GSBI_QUP_APSS_NS_REG(gsbi_id));
+	write32(GSBI_QUP_APSS_NS_REG(gsbi_id), reg_val);
 
 	reg_val |= (1 << GSBI_QUP_APPS_ROOT_ENA_SFT) |
 		   (1 << GSBI_QUP_APPS_MNCTR_EN_SFT);
-	writel(reg_val, GSBI_QUP_APSS_NS_REG(gsbi_id));
+	write32(GSBI_QUP_APSS_NS_REG(gsbi_id), reg_val);
 
 	reg_val |= (1 << GSBI_QUP_APPS_BRANCH_ENA_SFT);
-	writel(reg_val, GSBI_QUP_APSS_NS_REG(gsbi_id));
+	write32(GSBI_QUP_APSS_NS_REG(gsbi_id), reg_val);
 
 	/*Select i2c protocol*/
-	writel(((GSBI_CTL_PROTO_I2C & GSBI_CTL_PROTO_CODE_MSK) <<
-					GSBI_CTL_PROTO_CODE_SFT), gsbi_ctl);
+	write32(gsbi_ctl,
+		((GSBI_CTL_PROTO_I2C & GSBI_CTL_PROTO_CODE_MSK) << GSBI_CTL_PROTO_CODE_SFT));
 
 	return GSBI_SUCCESS;
 }
diff --git a/src/soc/qualcomm/ipq806x/lcc.c b/src/soc/qualcomm/ipq806x/lcc.c
index 978526d8e7..d577487618 100644
--- a/src/soc/qualcomm/ipq806x/lcc.c
+++ b/src/soc/qualcomm/ipq806x/lcc.c
@@ -129,43 +129,43 @@ static int lcc_init_enable_pll0(Ipq806xLccClocks *bus)
 
 	regval = 0;
 	regval = 15 << LCC_PLL0_L_SHIFT & LCC_PLL0_L_MASK;
-	writel(regval, &pll0_regs->l_val);
+	write32(&pll0_regs->l_val, regval);
 
 	regval = 0;
 	regval = 145 << LCC_PLL0_M_SHIFT & LCC_PLL0_M_MASK;
-	writel(regval, &pll0_regs->m_val);
+	write32(&pll0_regs->m_val, regval);
 
 	regval = 0;
 	regval = 199 << LCC_PLL0_N_SHIFT & LCC_PLL0_N_MASK;
-	writel(regval, &pll0_regs->n_val);
+	write32(&pll0_regs->n_val, regval);
 
 	regval = 0;
 	regval |= LCC_PLL0_CFG_LV_MAIN_ENABLE;
 	regval |= LCC_PLL0_CFG_FRAC_ENABLE;
-	writel(regval, &pll0_regs->config);
+	write32(&pll0_regs->config, regval);
 
 	regval = 0;
 	regval |= LCC_PLL_PCLK_SRC_PRI;
-	writel(regval, &pll_regs->pri);
+	write32(&pll_regs->pri, regval);
 
 	regval = 0;
 	regval |= 1 << LCC_PLL0_MODE_BIAS_CNT_SHIFT &
 			LCC_PLL0_MODE_BIAS_CNT_MASK;
 	regval |= 8 << LCC_PLL0_MODE_LOCK_CNT_SHIFT &
 			LCC_PLL0_MODE_LOCK_CNT_MASK;
-	writel(regval, &pll0_regs->mode);
+	write32(&pll0_regs->mode, regval);
 
-	regval = readl(&gcc_regs->apcs);
+	regval = read32(&gcc_regs->apcs);
 	regval |= GCC_PLL_APCS_PLL4_ENABLE;
-	writel(regval, &gcc_regs->apcs);
+	write32(&gcc_regs->apcs, regval);
 
-	regval = readl(&pll0_regs->mode);
+	regval = read32(&pll0_regs->mode);
 	regval |= LCC_PLL0_MODE_FSM_VOTE_ENABLE;
-	writel(regval, &pll0_regs->mode);
+	write32(&pll0_regs->mode, regval);
 
 	mdelay(1);
 
-	regval = readl(&pll0_regs->status);
+	regval = read32(&pll0_regs->status);
 	if (regval & LCC_PLL0_STAT_ACTIVE_MASK)
 		return 0;
 
@@ -182,7 +182,7 @@ static int lcc_init_enable_ahbix(Ipq806xLccClocks *bus)
 	regval |= 1 << LCC_AHBIX_MD_M_VAL_SHIFT & LCC_AHBIX_MD_M_VAL_MASK;
 	regval |= 252 << LCC_AHBIX_MD_NOT_2D_VAL_SHIFT &
 			LCC_AHBIX_MD_NOT_2D_VAL_MASK;
-	writel(regval, &ahbix_regs->md);
+	write32(&ahbix_regs->md, regval);
 
 	regval = 0;
 	regval |= 253 << LCC_AHBIX_NS_N_VAL_SHIFT & LCC_AHBIX_NS_N_VAL_MASK;
@@ -193,11 +193,11 @@ static int lcc_init_enable_ahbix(Ipq806xLccClocks *bus)
 	regval |= LCC_AHBIX_NS_MNC_MODE_DUAL;
 	regval |= LCC_AHBIX_NS_PREDIV_BYPASS;
 	regval |= LCC_AHBIX_NS_MN_SRC_LPA;
-	writel(regval, &ahbix_regs->ns);
+	write32(&ahbix_regs->ns, regval);
 
 	mdelay(1);
 
-	regval = readl(&ahbix_regs->status);
+	regval = read32(&ahbix_regs->status);
 	if (regval & LCC_AHBIX_STAT_AIF_CLK_MASK)
 		return 0;
 
@@ -248,7 +248,7 @@ static int lcc_init_mi2s(Ipq806xLccClocks *bus, unsigned freq)
 	regval |= m << LCC_MI2S_MD_M_VAL_SHIFT & LCC_MI2S_MD_M_VAL_MASK;
 	regval |= d << LCC_MI2S_MD_NOT_2D_VAL_SHIFT &
 			LCC_MI2S_MD_NOT_2D_VAL_MASK;
-	writel(regval, &mi2s_regs->md);
+	write32(&mi2s_regs->md, regval);
 
 	regval = 0;
 	regval |= n << LCC_MI2S_NS_N_VAL_SHIFT & LCC_MI2S_NS_N_VAL_MASK;
@@ -258,7 +258,7 @@ static int lcc_init_mi2s(Ipq806xLccClocks *bus, unsigned freq)
 	regval |= LCC_MI2S_NS_MNC_MODE_DUAL;
 	regval |= pd;
 	regval |= LCC_MI2S_NS_MN_SRC_LPA;
-	writel(regval, &mi2s_regs->ns);
+	write32(&mi2s_regs->ns, regval);
 
 	return 0;
 }
@@ -268,14 +268,14 @@ static int lcc_enable_mi2s(Ipq806xLccClocks *bus)
 	Ipq806xLccMi2sRegs *mi2s_regs = bus->lcc_mi2s_regs;
 	uint32_t regval;
 
-	regval = readl(&mi2s_regs->ns);
+	regval = read32(&mi2s_regs->ns);
 	regval |= LCC_MI2S_NS_OSR_CXC_ENABLE;
 	regval |= LCC_MI2S_NS_BIT_CXC_ENABLE;
-	writel(regval, &mi2s_regs->ns);
+	write32(&mi2s_regs->ns, regval);
 
 	udelay(10);
 
-	regval = readl(&mi2s_regs->status);
+	regval = read32(&mi2s_regs->status);
 	if (regval & LCC_MI2S_STAT_OSR_CLK_MASK)
 		if (regval & LCC_MI2S_STAT_BIT_CLK_MASK)
 			return 0;
diff --git a/src/soc/qualcomm/ipq806x/qup.c b/src/soc/qualcomm/ipq806x/qup.c
index 25adfc18db..bc78e7c67a 100644
--- a/src/soc/qualcomm/ipq806x/qup.c
+++ b/src/soc/qualcomm/ipq806x/qup.c
@@ -51,9 +51,9 @@ static unsigned gsbi_qup_base[] = {
 
 static qup_return_t qup_i2c_master_status(gsbi_id_t gsbi_id)
 {
-	uint32_t reg_val = readl(QUP_ADDR(gsbi_id, QUP_I2C_MASTER_STATUS));
+	uint32_t reg_val = read32(QUP_ADDR(gsbi_id, QUP_I2C_MASTER_STATUS));
 
-	if (readl(QUP_ADDR(gsbi_id, QUP_ERROR_FLAGS)))
+	if (read32(QUP_ADDR(gsbi_id, QUP_ERROR_FLAGS)))
 		return QUP_ERR_XFER_FAIL;
 	if (reg_val & QUP_I2C_INVALID_READ_ADDR)
 		return QUP_ERR_I2C_INVALID_SLAVE_ADDR;
@@ -77,7 +77,7 @@ static int check_bit_state(uint32_t *reg, int wait_for)
 {
 	unsigned int count = TIMEOUT_CNT;
 
-	while ((readl(reg) & (QUP_STATE_VALID_MASK | QUP_STATE_MASK)) !=
+	while ((read32(reg) & (QUP_STATE_VALID_MASK | QUP_STATE_MASK)) !=
 			(QUP_STATE_VALID | wait_for)) {
 		if (count == 0)
 			return QUP_ERR_TIMEOUT;
@@ -103,14 +103,14 @@ qup_return_t qup_reset_i2c_master_status(gsbi_id_t gsbi_id)
 	 * Bit31-25, Bit1 and Bit0 are reserved.
 	 */
 	//TODO: Define each status bit. OR all status bits in a single macro.
-	writel(0x3FFFFFC, QUP_ADDR(gsbi_id, QUP_I2C_MASTER_STATUS));
+	write32(QUP_ADDR(gsbi_id, QUP_I2C_MASTER_STATUS), 0x3FFFFFC);
 	return QUP_SUCCESS;
 }
 
 static qup_return_t qup_reset_master_status(gsbi_id_t gsbi_id)
 {
-	writel(0x7C, QUP_ADDR(gsbi_id, QUP_ERROR_FLAGS));
-	writel(0x7C, QUP_ADDR(gsbi_id, QUP_ERROR_FLAGS_EN));
+	write32(QUP_ADDR(gsbi_id, QUP_ERROR_FLAGS), 0x7C);
+	write32(QUP_ADDR(gsbi_id, QUP_ERROR_FLAGS_EN), 0x7C);
 	qup_reset_i2c_master_status(gsbi_id);
 	return QUP_SUCCESS;
 }
@@ -120,7 +120,7 @@ static qup_return_t qup_fifo_wait_for(gsbi_id_t gsbi_id, uint32_t status)
 	qup_return_t ret = QUP_ERR_UNDEFINED;
 	unsigned int count = TIMEOUT_CNT;
 
-	while (!(readl(QUP_ADDR(gsbi_id, QUP_OPERATIONAL)) & status)) {
+	while (!(read32(QUP_ADDR(gsbi_id, QUP_OPERATIONAL)) & status)) {
 		ret = qup_i2c_master_status(gsbi_id);
 		if (ret)
 			return ret;
@@ -137,7 +137,7 @@ static qup_return_t qup_fifo_wait_while(gsbi_id_t gsbi_id, uint32_t status)
 	qup_return_t ret = QUP_ERR_UNDEFINED;
 	unsigned int count = TIMEOUT_CNT;
 
-	while (readl(QUP_ADDR(gsbi_id, QUP_OPERATIONAL)) & status) {
+	while (read32(QUP_ADDR(gsbi_id, QUP_OPERATIONAL)) & status) {
 		ret = qup_i2c_master_status(gsbi_id);
 		if (ret)
 			return ret;
@@ -161,16 +161,16 @@ static qup_return_t qup_i2c_write_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj,
 	qup_reset_master_status(gsbi_id);
 	qup_set_state(gsbi_id, QUP_STATE_RUN);
 
-	writel((QUP_I2C_START_SEQ | QUP_I2C_ADDR(addr)),
-	       QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO));
+	write32(QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO),
+		(QUP_I2C_START_SEQ | QUP_I2C_ADDR(addr)));
 
 	while (data_len) {
 		if (data_len == 1 && stop_seq) {
-			writel((QUP_I2C_STOP_SEQ | QUP_I2C_DATA(data_ptr[idx])),
-			       QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO));
+			write32(QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO),
+				(QUP_I2C_STOP_SEQ | QUP_I2C_DATA(data_ptr[idx])));
 		} else {
-			writel((QUP_I2C_DATA_SEQ | QUP_I2C_DATA(data_ptr[idx])),
-			       QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO));
+			write32(QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO),
+				(QUP_I2C_DATA_SEQ | QUP_I2C_DATA(data_ptr[idx])));
 		}
 		data_len--;
 		idx++;
@@ -187,10 +187,10 @@ static qup_return_t qup_i2c_write_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj,
 			means that software knows to return to fill the output
 			FIFO with data.
 		 */
-		if (readl(QUP_ADDR(gsbi_id, QUP_OPERATIONAL)) &
+		if (read32(QUP_ADDR(gsbi_id, QUP_OPERATIONAL)) &
 				OUTPUT_SERVICE_FLAG) {
-			writel(OUTPUT_SERVICE_FLAG,
-			       QUP_ADDR(gsbi_id, QUP_OPERATIONAL));
+			write32(QUP_ADDR(gsbi_id, QUP_OPERATIONAL),
+				OUTPUT_SERVICE_FLAG);
 		}
 	}
 
@@ -234,17 +234,17 @@ static qup_return_t qup_i2c_read_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj)
 	qup_reset_master_status(gsbi_id);
 	qup_set_state(gsbi_id, QUP_STATE_RUN);
 
-	writel((QUP_I2C_START_SEQ | (QUP_I2C_ADDR(addr) | QUP_I2C_SLAVE_READ)),
-	       QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO));
+	write32(QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO),
+		(QUP_I2C_START_SEQ | (QUP_I2C_ADDR(addr) | QUP_I2C_SLAVE_READ)));
 
-	writel((QUP_I2C_RECV_SEQ | data_len),
-	       QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO));
+	write32(QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO),
+		(QUP_I2C_RECV_SEQ | data_len));
 
 	ret = qup_fifo_wait_while(gsbi_id, OUTPUT_FIFO_NOT_EMPTY);
 	if (ret)
 		return ret;
 
-	writel(OUTPUT_SERVICE_FLAG, QUP_ADDR(gsbi_id, QUP_OPERATIONAL));
+	write32(QUP_ADDR(gsbi_id, QUP_OPERATIONAL), OUTPUT_SERVICE_FLAG);
 
 	while (data_len) {
 		uint32_t data;
@@ -253,7 +253,7 @@ static qup_return_t qup_i2c_read_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj)
 		if (ret)
 			return ret;
 
-		data = readl(QUP_ADDR(gsbi_id, QUP_INPUT_FIFO));
+		data = read32(QUP_ADDR(gsbi_id, QUP_INPUT_FIFO));
 
 		/*
 		 * Process tag and corresponding data value. For I2C master
@@ -268,8 +268,8 @@ static qup_return_t qup_i2c_read_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj)
 			data_ptr[idx] = QUP_I2C_DATA(data);
 			idx++;
 			data_len--;
-			writel(INPUT_SERVICE_FLAG,
-			       QUP_ADDR(gsbi_id, QUP_OPERATIONAL));
+			write32(QUP_ADDR(gsbi_id, QUP_OPERATIONAL),
+				INPUT_SERVICE_FLAG);
 		} else if (QUP_I2C_MI_TAG(data) == QUP_I2C_MISTOP_SEQ) {
 			/* Tag: MISTOP: Last byte of master input. */
 			data_ptr[idx] = QUP_I2C_DATA(data);
@@ -282,7 +282,7 @@ static qup_return_t qup_i2c_read_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj)
 		}
 	}
 
-	writel(INPUT_SERVICE_FLAG, QUP_ADDR(gsbi_id, QUP_OPERATIONAL));
+	write32(QUP_ADDR(gsbi_id, QUP_OPERATIONAL), INPUT_SERVICE_FLAG);
 	p_tx_obj->p.iic.data_len = idx;
 	qup_set_state(gsbi_id, QUP_STATE_PAUSE);
 
@@ -316,7 +316,7 @@ qup_return_t qup_init(gsbi_id_t gsbi_id, const qup_config_t *config_ptr)
 	uint32_t reg_val;
 
 	/* Reset the QUP core.*/
-	writel(0x1, QUP_ADDR(gsbi_id, QUP_SW_RESET));
+	write32(QUP_ADDR(gsbi_id, QUP_SW_RESET), 0x1);
 
 	/*Wait till the reset takes effect */
 	ret = qup_wait_for_state(gsbi_id, QUP_STATE_RESET);
@@ -324,7 +324,7 @@ qup_return_t qup_init(gsbi_id_t gsbi_id, const qup_config_t *config_ptr)
 		goto bailout;
 
 	/* Reset the config */
-	writel(0, QUP_ADDR(gsbi_id, QUP_CONFIG));
+	write32(QUP_ADDR(gsbi_id, QUP_CONFIG), 0);
 
 	/*Program the config register*/
 	/*Set N value*/
@@ -340,10 +340,10 @@ qup_return_t qup_init(gsbi_id_t gsbi_id, const qup_config_t *config_ptr)
 		ret = QUP_ERR_UNSUPPORTED;
 		goto bailout;
 	}
-	writel(reg_val, QUP_ADDR(gsbi_id, QUP_CONFIG));
+	write32(QUP_ADDR(gsbi_id, QUP_CONFIG), reg_val);
 
 	/*Reset i2c clk cntl register*/
-	writel(0, QUP_ADDR(gsbi_id, QUP_I2C_MASTER_CLK_CTL));
+	write32(QUP_ADDR(gsbi_id, QUP_I2C_MASTER_CLK_CTL), 0);
 
 	/*Set QUP IO Mode*/
 	switch (config_ptr->mode) {
@@ -358,14 +358,14 @@ qup_return_t qup_init(gsbi_id_t gsbi_id, const qup_config_t *config_ptr)
 		ret = QUP_ERR_UNSUPPORTED;
 		goto bailout;
 	}
-	writel(reg_val, QUP_ADDR(gsbi_id, QUP_IO_MODES));
+	write32(QUP_ADDR(gsbi_id, QUP_IO_MODES), reg_val);
 
 	/*Set i2c clk cntl*/
 	reg_val = (QUP_DIVIDER_MIN_VAL << QUP_HS_DIVIDER_SHFT);
 	reg_val |= ((((config_ptr->src_frequency / config_ptr->clk_frequency)
 			/ 2) - QUP_DIVIDER_MIN_VAL) &
 				QUP_FS_DIVIDER_MASK);
-	writel(reg_val, QUP_ADDR(gsbi_id, QUP_I2C_MASTER_CLK_CTL));
+	write32(QUP_ADDR(gsbi_id, QUP_I2C_MASTER_CLK_CTL), reg_val);
 
 bailout:
 	if (ret)
@@ -377,7 +377,7 @@ bailout:
 qup_return_t qup_set_state(gsbi_id_t gsbi_id, uint32_t state)
 {
 	qup_return_t ret = QUP_ERR_UNDEFINED;
-	unsigned curr_state = readl(QUP_ADDR(gsbi_id, QUP_STATE));
+	unsigned curr_state = read32(QUP_ADDR(gsbi_id, QUP_STATE));
 
 	if ((state >= QUP_STATE_RESET && state <= QUP_STATE_PAUSE)
 		&& (curr_state & QUP_STATE_VALID_MASK)) {
@@ -387,10 +387,10 @@ qup_return_t qup_set_state(gsbi_id_t gsbi_id, uint32_t state)
 		* transition to complete.
 		*/
 		if (QUP_STATE_PAUSE == curr_state && QUP_STATE_RESET == state) {
-			writel(0x2, QUP_ADDR(gsbi_id, QUP_STATE));
-			writel(0x2, QUP_ADDR(gsbi_id, QUP_STATE));
+			write32(QUP_ADDR(gsbi_id, QUP_STATE), 0x2);
+			write32(QUP_ADDR(gsbi_id, QUP_STATE), 0x2);
 		} else {
-			writel(state, QUP_ADDR(gsbi_id, QUP_STATE));
+			write32(QUP_ADDR(gsbi_id, QUP_STATE), state);
 		}
 		ret = qup_wait_for_state(gsbi_id, state);
 	}
@@ -402,7 +402,7 @@ static qup_return_t qup_i2c_send_data(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj,
 				      uint8_t stop_seq)
 {
 	qup_return_t ret = QUP_ERR_UNDEFINED;
-	uint8_t mode = (readl(QUP_ADDR(gsbi_id, QUP_IO_MODES)) >>
+	uint8_t mode = (read32(QUP_ADDR(gsbi_id, QUP_IO_MODES)) >>
 			QUP_OUTPUT_MODE_SHFT) & QUP_MODE_MASK;
 
 	ret = qup_i2c_write(gsbi_id, mode, p_tx_obj, stop_seq);
@@ -423,7 +423,7 @@ qup_return_t qup_send_data(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj,
 {
 	qup_return_t ret = QUP_ERR_UNDEFINED;
 
-	if (p_tx_obj->protocol == ((readl(QUP_ADDR(gsbi_id, QUP_CONFIG)) >>
+	if (p_tx_obj->protocol == ((read32(QUP_ADDR(gsbi_id, QUP_CONFIG)) >>
 			QUP_MINI_CORE_PROTO_SHFT) & QUP_MINI_CORE_PROTO_MASK)) {
 		switch (p_tx_obj->protocol) {
 		case QUP_MINICORE_I2C_MASTER:
@@ -440,7 +440,7 @@ qup_return_t qup_send_data(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj,
 static qup_return_t qup_i2c_recv_data(gsbi_id_t gsbi_id, qup_data_t *p_rx_obj)
 {
 	qup_return_t ret = QUP_ERR_UNDEFINED;
-	uint8_t mode = (readl(QUP_ADDR(gsbi_id, QUP_IO_MODES)) >>
+	uint8_t mode = (read32(QUP_ADDR(gsbi_id, QUP_IO_MODES)) >>
 			QUP_INPUT_MODE_SHFT) & QUP_MODE_MASK;
 
 	ret = qup_i2c_read(gsbi_id, mode, p_rx_obj);
@@ -460,7 +460,7 @@ qup_return_t qup_recv_data(gsbi_id_t gsbi_id, qup_data_t *p_rx_obj)
 {
 	qup_return_t ret = QUP_ERR_UNDEFINED;
 
-	if (p_rx_obj->protocol == ((readl(QUP_ADDR(gsbi_id, QUP_CONFIG)) >>
+	if (p_rx_obj->protocol == ((read32(QUP_ADDR(gsbi_id, QUP_CONFIG)) >>
 			QUP_MINI_CORE_PROTO_SHFT) & QUP_MINI_CORE_PROTO_MASK)) {
 		switch (p_rx_obj->protocol) {
 		case QUP_MINICORE_I2C_MASTER:
diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c
index b374f17537..4a353130e1 100644
--- a/src/soc/qualcomm/ipq806x/spi.c
+++ b/src/soc/qualcomm/ipq806x/spi.c
@@ -285,7 +285,7 @@ static void CS_change(int port_num, int cs_num, int enable)
 	val &= (~(1 << GPIO_OUTPUT));
 	if (!enable)
 		val |= (1 << GPIO_OUTPUT);
-	writel(val, addr);
+	write32(addr, val);
 }
 
 /*
diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c
index ebe1913734..c9ef77014c 100644
--- a/src/soc/qualcomm/ipq806x/uart.c
+++ b/src/soc/qualcomm/ipq806x/uart.c
@@ -89,22 +89,22 @@ static const uart_params_t uart_board_param = {
 static unsigned int msm_boot_uart_dm_init_rx_transfer(void *uart_dm_base)
 {
 	/* Reset receiver */
-	writel(MSM_BOOT_UART_DM_CMD_RESET_RX,
-		MSM_BOOT_UART_DM_CR(uart_dm_base));
+	write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
+		MSM_BOOT_UART_DM_CMD_RESET_RX);
 
 	/* Enable receiver */
-	writel(MSM_BOOT_UART_DM_CR_RX_ENABLE,
-		MSM_BOOT_UART_DM_CR(uart_dm_base));
-	writel(MSM_BOOT_UART_DM_DMRX_DEF_VALUE,
-		MSM_BOOT_UART_DM_DMRX(uart_dm_base));
+	write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
+		MSM_BOOT_UART_DM_CR_RX_ENABLE);
+	write32(MSM_BOOT_UART_DM_DMRX(uart_dm_base),
+		MSM_BOOT_UART_DM_DMRX_DEF_VALUE);
 
 	/* Clear stale event */
-	writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT,
-		MSM_BOOT_UART_DM_CR(uart_dm_base));
+	write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
+		MSM_BOOT_UART_DM_CMD_RES_STALE_INT);
 
 	/* Enable stale event */
-	writel(MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT,
-		MSM_BOOT_UART_DM_CR(uart_dm_base));
+	write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
+		MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT);
 
 	return MSM_BOOT_UART_DM_E_SUCCESS;
 }
@@ -200,17 +200,17 @@ void uart_tx_byte(int idx, unsigned char data)
 	void *base = uart_board_param.uart_dm_base;
 
 	/* Wait until transmit FIFO is empty. */
-	while (!(readl(MSM_BOOT_UART_DM_SR(base)) &
+	while (!(read32(MSM_BOOT_UART_DM_SR(base)) &
 		 MSM_BOOT_UART_DM_SR_TXEMT))
 		udelay(1);
 	/*
 	 * TX FIFO is ready to accept new character(s). First write number of
 	 * characters to be transmitted.
 	 */
-	writel(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base));
+	write32(MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base), num_of_chars);
 
 	/* And now write the character(s) */
-	writel(tx_data, MSM_BOOT_UART_DM_TF(base, 0));
+	write32(MSM_BOOT_UART_DM_TF(base, 0), tx_data);
 }
 #endif /* CONFIG_SERIAL_UART */
 
@@ -220,12 +220,12 @@ void uart_tx_byte(int idx, unsigned char data)
  */
 static unsigned int msm_boot_uart_dm_reset(void *base)
 {
-	writel(MSM_BOOT_UART_DM_CMD_RESET_RX, MSM_BOOT_UART_DM_CR(base));
-	writel(MSM_BOOT_UART_DM_CMD_RESET_TX, MSM_BOOT_UART_DM_CR(base));
-	writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT,
-		 MSM_BOOT_UART_DM_CR(base));
-	writel(MSM_BOOT_UART_DM_CMD_RES_TX_ERR, MSM_BOOT_UART_DM_CR(base));
-	writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(base));
+	write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_RX);
+	write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_TX);
+	write32(MSM_BOOT_UART_DM_CR(base),
+		MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT);
+	write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_TX_ERR);
+	write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_STALE_INT);
 
 	return MSM_BOOT_UART_DM_E_SUCCESS;
 }
@@ -238,40 +238,40 @@ static unsigned int msm_boot_uart_dm_init(void  *uart_dm_base)
 {
 	/* Configure UART mode registers MR1 and MR2 */
 	/* Hardware flow control isn't supported */
-	writel(0x0, MSM_BOOT_UART_DM_MR1(uart_dm_base));
+	write32(MSM_BOOT_UART_DM_MR1(uart_dm_base), 0x0);
 
 	/* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */
-	writel(MSM_BOOT_UART_DM_8_N_1_MODE,
-		 MSM_BOOT_UART_DM_MR2(uart_dm_base));
+	write32(MSM_BOOT_UART_DM_MR2(uart_dm_base),
+		MSM_BOOT_UART_DM_8_N_1_MODE);
 
 	/* Configure Interrupt Mask register IMR */
-	writel(MSM_BOOT_UART_DM_IMR_ENABLED,
-		 MSM_BOOT_UART_DM_IMR(uart_dm_base));
+	write32(MSM_BOOT_UART_DM_IMR(uart_dm_base),
+		MSM_BOOT_UART_DM_IMR_ENABLED);
 
 	/*
 	 * Configure Tx and Rx watermarks configuration registers
 	 * TX watermark value is set to 0 - interrupt is generated when
 	 * FIFO level is less than or equal to 0
 	 */
-	writel(MSM_BOOT_UART_DM_TFW_VALUE,
-		 MSM_BOOT_UART_DM_TFWR(uart_dm_base));
+	write32(MSM_BOOT_UART_DM_TFWR(uart_dm_base),
+		MSM_BOOT_UART_DM_TFW_VALUE);
 
 	/* RX watermark value */
-	writel(MSM_BOOT_UART_DM_RFW_VALUE,
-		 MSM_BOOT_UART_DM_RFWR(uart_dm_base));
+	write32(MSM_BOOT_UART_DM_RFWR(uart_dm_base),
+		MSM_BOOT_UART_DM_RFW_VALUE);
 
 	/* Configure Interrupt Programming Register */
 	/* Set initial Stale timeout value */
-	writel(MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB,
-		MSM_BOOT_UART_DM_IPR(uart_dm_base));
+	write32(MSM_BOOT_UART_DM_IPR(uart_dm_base),
+		MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB);
 
 	/* Configure IRDA if required */
 	/* Disabling IRDA mode */
-	writel(0x0, MSM_BOOT_UART_DM_IRDA(uart_dm_base));
+	write32(MSM_BOOT_UART_DM_IRDA(uart_dm_base), 0x0);
 
 	/* Configure hunt character value in HCR register */
 	/* Keep it in reset state */
-	writel(0x0, MSM_BOOT_UART_DM_HCR(uart_dm_base));
+	write32(MSM_BOOT_UART_DM_HCR(uart_dm_base), 0x0);
 
 	/*
 	 * Configure Rx FIFO base address
@@ -286,11 +286,11 @@ static unsigned int msm_boot_uart_dm_init(void  *uart_dm_base)
 
 	/* Enable/Disable Rx/Tx DM interfaces */
 	/* Data Mover not currently utilized. */
-	writel(0x0, MSM_BOOT_UART_DM_DMEN(uart_dm_base));
+	write32(MSM_BOOT_UART_DM_DMEN(uart_dm_base), 0x0);
 
 	/* Enable transmitter */
-	writel(MSM_BOOT_UART_DM_CR_TX_ENABLE,
-		MSM_BOOT_UART_DM_CR(uart_dm_base));
+	write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
+		MSM_BOOT_UART_DM_CR_TX_ENABLE);
 
 	/* Initialize Receive Path */
 	msm_boot_uart_dm_init_rx_transfer(uart_dm_base);
@@ -311,7 +311,7 @@ void uart_init(int idx)
 
 	dm_base = uart_board_param.uart_dm_base;
 
-	if (readl(MSM_BOOT_UART_DM_CSR(dm_base)) == UART_DM_CLK_RX_TX_BIT_RATE)
+	if (read32(MSM_BOOT_UART_DM_CSR(dm_base)) == UART_DM_CLK_RX_TX_BIT_RATE)
 		return; /* UART must have been already initialized. */
 
 	gsbi_base = uart_board_param.uart_gsbi_base;
@@ -325,10 +325,9 @@ void uart_init(int idx)
 		uart_board_param.mnd_value.d_value,
 		0);
 
-	writel(GSBI_PROTOCOL_CODE_I2C_UART <<
-		GSBI_CTRL_REG_PROTOCOL_CODE_S,
-		GSBI_CTRL_REG(gsbi_base));
-	writel(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(dm_base));
+	write32(GSBI_CTRL_REG(gsbi_base),
+		GSBI_PROTOCOL_CODE_I2C_UART << GSBI_CTRL_REG_PROTOCOL_CODE_S);
+	write32(MSM_BOOT_UART_DM_CSR(dm_base), UART_DM_CLK_RX_TX_BIT_RATE);
 
 	/* Intialize UART_DM */
 	msm_boot_uart_dm_init(dm_base);
@@ -355,7 +354,7 @@ void uart_tx_flush(int idx)
 {
 	void *base = uart_board_param.uart_dm_base;
 
-	while (!(readl(MSM_BOOT_UART_DM_SR(base)) &
+	while (!(read32(MSM_BOOT_UART_DM_SR(base)) &
 		 MSM_BOOT_UART_DM_SR_TXEMT))
 		;
 }
diff --git a/src/soc/qualcomm/ipq806x/usb.c b/src/soc/qualcomm/ipq806x/usb.c
index 69b3998624..d7dac7243c 100644
--- a/src/soc/qualcomm/ipq806x/usb.c
+++ b/src/soc/qualcomm/ipq806x/usb.c
@@ -101,16 +101,16 @@ static struct usb_dwc3 * const usb_host2_dwc3 = (void *)USB_HOST2_DWC3_BASE;
 
 static void setup_dwc3(struct usb_dwc3 *dwc3)
 {
-	writel(0x1 << 31 | 0x1 << 25 | 0x1 << 24 | 0x1 << 19 | 0x1 << 18 | 0x1 << 1 | 0x1 << 0 | 0,
-	       &dwc3->usb3pipectl);
+	write32(&dwc3->usb3pipectl,
+		0x1 << 31 | 0x1 << 25 | 0x1 << 24 | 0x1 << 19 | 0x1 << 18 | 0x1 << 1 | 0x1 << 0 | 0);
 
-	writel(0x1 << 31 | 0x9 << 10 | 0x1 << 8 | 0x1 << 6 | 0,
-	       &dwc3->usb2phycfg);
+	write32(&dwc3->usb2phycfg,
+		0x1 << 31 | 0x9 << 10 | 0x1 << 8 | 0x1 << 6 | 0);
 
-	writel(0x2 << 19 | 0x1 << 16 | 0x1 << 12 | 0x1 << 11 | 0x1 << 10 | 0x1 << 2 | 0,
-	       &dwc3->ctl);
+	write32(&dwc3->ctl,
+		0x2 << 19 | 0x1 << 16 | 0x1 << 12 | 0x1 << 11 | 0x1 << 10 | 0x1 << 2 | 0);
 
-	writel(0x32 << 22 | 0x1 << 15 | 0x10 << 0 | 0, &dwc3->uctl);
+	write32(&dwc3->uctl, 0x32 << 22 | 0x1 << 15 | 0x10 << 0 | 0);
 
 	udelay(5);
 
@@ -121,16 +121,16 @@ static void setup_dwc3(struct usb_dwc3 *dwc3)
 
 static void setup_phy(struct usb_qc_phy *phy)
 {
-	writel(0x1 << 24 | 0x1 << 8 | 0x1 << 7 | 0x19 << 0 | 0,
-	       &phy->ss_phy_ctrl);
+	write32(&phy->ss_phy_ctrl,
+		0x1 << 24 | 0x1 << 8 | 0x1 << 7 | 0x19 << 0 | 0);
 
-	writel(0x1 << 26 | 0x1 << 25 | 0x1 << 24 | 0x1 << 21 | 0x1 << 20 | 0x1 << 18 | 0x1 << 17 | 0x1 << 11 | 0x1 << 9 | 0x1 << 8 | 0x1 << 7 | 0x7 << 4 | 0x1 << 1 | 0,
-	       &phy->hs_phy_ctrl);
+	write32(&phy->hs_phy_ctrl,
+		0x1 << 26 | 0x1 << 25 | 0x1 << 24 | 0x1 << 21 | 0x1 << 20 | 0x1 << 18 | 0x1 << 17 | 0x1 << 11 | 0x1 << 9 | 0x1 << 8 | 0x1 << 7 | 0x7 << 4 | 0x1 << 1 | 0);
 
-	writel(0x6e << 20 | 0x20 << 14 | 0x17 << 8 | 0x9 << 3 | 0,
-	       &phy->ss_phy_param1);
+	write32(&phy->ss_phy_param1,
+		0x6e << 20 | 0x20 << 14 | 0x17 << 8 | 0x9 << 3 | 0);
 
-	writel(0x1 << 2, &phy->general_cfg);	/* set XHCI 1.00 compliance */
+	write32(&phy->general_cfg, 0x1 << 2);	/* set XHCI 1.00 compliance */
 
 	udelay(5);
 	clrbits_le32(&phy->ss_phy_ctrl, 0x1 << 7); /* deassert SS PHY reset */
@@ -141,9 +141,9 @@ static void crport_handshake(void *capture_reg, void *acknowledge_bit, u32 data)
 	int usec = 100;
 
 	if (capture_reg)
-		writel(data, capture_reg);
+		write32(capture_reg, data);
 
-	writel(0x1 << 0, acknowledge_bit);
+	write32(acknowledge_bit, 0x1 << 0);
 	while (read32(acknowledge_bit) && --usec)
 		udelay(1);