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| author | yolkshih <yolkshih@ami.corp-partner.google.com> | 2021-04-19 18:41:26 +0800 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2021-04-24 00:24:00 +0000 |
| commit | 3827e03ee2d9b51ccf12bdc6cf68f3c678d8759c (patch) | |
| tree | 1065b546ce83a932ada650d7e49633445e25d0f3 /src/soc/qualcomm | |
| parent | 0ced2e85ba61e0ee859e4ba04cbe8a3dcccd20ac (diff) | |
| download | coreboot-3827e03ee2d9b51ccf12bdc6cf68f3c678d8759c.tar.xz | |
Coachz: Observe SPI_CLK voltage level is only 1.4V, need to adjust
the signal integrity strength to correct voltage level 1.8V
BUG=b:184714790
BRANCH=trogdor
TEST=HW test
Change-Id: Iee7b458b6aa7d701724da87ecdf0f993d0565c0c
Signed-off-by: yolkshih <yolkshih@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wenchao Han <hanwenchao@huaqin.corp-partner.google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/qualcomm')
| -rw-r--r-- | src/soc/qualcomm/sc7180/qspi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/qualcomm/sc7180/qspi.c b/src/soc/qualcomm/sc7180/qspi.c index 675641bc4c..c1e9779736 100644 --- a/src/soc/qualcomm/sc7180/qspi.c +++ b/src/soc/qualcomm/sc7180/qspi.c @@ -152,7 +152,7 @@ static void configure_gpios(void) GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); gpio_configure(GPIO(63), GPIO63_FUNC_QSPI_CLK, - GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); + GPIO_NO_PULL, GPIO_8MA, GPIO_OUTPUT_ENABLE); } static void queue_bounce_data(uint8_t *data, uint32_t data_bytes, |