diff options
| author | Mary Ruthven <mruthven@chromium.org> | 2015-11-13 14:05:27 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-12-03 14:17:04 +0100 |
| commit | f82e8ab6970f0f18d81e3da61a96a955987f5362 (patch) | |
| tree | 6e9567912ec15b0f31f8f6018fadf792827c6552 /src/soc/qualcomm | |
| parent | 857829654c6e519a2165916d6596b5060b7b6aca (diff) | |
| download | coreboot-f82e8ab6970f0f18d81e3da61a96a955987f5362.tar.xz | |
cbfs_spi: enable CBFS access in early romstage
Currently the CBFS mmap cannot be accessed at the beginning of romstage
because it waits until DRAM is initialized. This change first loads CBFS
into SRAM and then switches to using DRAM as the backing once it is
initialized.
BUG=chromium:210230
BRANCH=none
TEST=confirm that the cbfs can be access at the beginning and end of
romstage on different boards.
Change-Id: I9fdaef392349c27ba1c19d4cd07e8ee0ac92dddc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ccaaba266386c7d5cc62de63bdca81a0cc7c4d83
Original-Change-Id: Idabfab99765b52069755e1d1aa61bbee39501796
Original-Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312577
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12586
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm')
| -rw-r--r-- | src/soc/qualcomm/ipq806x/include/soc/memlayout.ld | 15 |
1 files changed, 2 insertions, 13 deletions
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld index 60fb5822cd..6ff2b77608 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld @@ -38,16 +38,7 @@ SECTIONS QCA_SHARED_RAM(2A03F000, 4K) */ STACK(0x2A040000, 16K) -#ifdef __PRE_RAM__ - /* - * ipq8064 is different from most other ARM platforms: it loads the - * proprietary DRAM initialization code from CBFS (as opposed to compiling - * it in into rombase). As a result CBFS needs to be used before DRAM is - * availale, which means CBFS cache must be in SRAM, which in turn means - * that PRERAM_CBFS_CACHE description can not be used here. - */ - CBFS_CACHE(0x2A044000, 93K) -#endif + PRERAM_CBFS_CACHE(0x2A044000, 93K) TTB_SUBTABLES(0x2A05B800, 2K) TTB(0x2A05C000, 16K) SRAM_END(0x2A060000) @@ -55,8 +46,6 @@ SECTIONS DRAM_START(0x40000000) RAMSTAGE(0x40640000, 128K) SYMBOL(memlayout_cbmem_top, 0x59F80000) -#ifndef __PRE_RAM__ - CBFS_CACHE(0x59F80000, 384K) -#endif + POSTRAM_CBFS_CACHE(0x59F80000, 384K) DMA_COHERENT(0x5A000000, 2M) } |