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| author | Vadim Bendebury <vbendeb@chromium.org> | 2014-05-23 14:18:35 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-01-04 00:27:50 +0100 |
| commit | 11aaf1f42ad8035c2870dc50852437f5e8863061 (patch) | |
| tree | 5b39011faeed8d3601e5449f9a9c62093cd06a81 /src/soc/qualcomm | |
| parent | 66fdbced5e61ad2387bfae2db7caf507fef88f37 (diff) | |
| download | coreboot-11aaf1f42ad8035c2870dc50852437f5e8863061.tar.xz | |
ipq8064: Add work around for slow timer clock
Libpayload libc requires timer clock frequency to be at least 1MHz.
Ipq8064 code presently provides a single option of 32kHz. Pretend to
be running at 1 MHz without additional accuracy.
This is a hack which will be reverted as soon as the SOC is configured
to supply a faster running clock.
BUG=chrome-os-partner:27784, chrome-os-partner:28880
TEST=with other changes depthcharge boots to the CLI console
Original-Change-Id: I80ec6652bc5693a549668cd6e824e9cf5c26b182
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201342
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 466a59967b13986099106f8b44924648c1e6e6cd)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I113689191db70710e7a45ccd02d672f482343e35
Reviewed-on: http://review.coreboot.org/8004
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/qualcomm')
0 files changed, 0 insertions, 0 deletions