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authorVaradarajan Narayanan <varada@codeaurora.org>2015-10-01 16:11:29 +0530
committerPatrick Georgi <pgeorgi@google.com>2016-05-10 23:12:42 +0200
commit520d5fb4272e8f80aef9904dc06c5c5083799d9b (patch)
tree2047f553f337fdc9dc63ccae6bcb8f3e1ccdc8ab /src/soc/qualcomm
parentad8c35c8eee347e7f8f987655538ee0a7850da64 (diff)
downloadcoreboot-520d5fb4272e8f80aef9904dc06c5c5083799d9b.tar.xz
soc/qualcomm/ipq40xx: Fix GPIO no.s for BGA part
BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Change-Id: I7c58fe7dc0132e8c01163fc049217f07081c658a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d746b667e309fd8eec62cf84e4ea4006ab2984f0 Original-Change-Id: Idcb3189a812e75815eb15a61c1de273b5e218875 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333305 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14669 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/qualcomm')
-rw-r--r--src/soc/qualcomm/ipq40xx/Kconfig4
-rw-r--r--src/soc/qualcomm/ipq40xx/uart.c10
2 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig
index 37046cae70..9817c1f17c 100644
--- a/src/soc/qualcomm/ipq40xx/Kconfig
+++ b/src/soc/qualcomm/ipq40xx/Kconfig
@@ -17,6 +17,10 @@ config CHROMEOS
select SEPARATE_VERSTAGE
select RETURN_FROM_VERSTAGE
+config IPQ_QFN_PART
+ bool "Is the SoC a BGA part or QFN part"
+ default n
+
config MBN_ENCAPSULATION
depends on USE_BLOBS
bool "bootblock encapsulation for ipq40xx"
diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c
index 81b2281a86..0f8add5501 100644
--- a/src/soc/qualcomm/ipq40xx/uart.c
+++ b/src/soc/qualcomm/ipq40xx/uart.c
@@ -59,15 +59,25 @@ static const uart_params_t uart_board_param = {
.blsp_uart = BLSP1_UART1,
.dbg_uart_gpio = {
{
+#if IS_ENABLED(CONFIG_IPQ_QFN_PART)
.gpio = 60,
.func = 2,
+#else /* bga */
+ .gpio = 16,
+ .func = 1,
+#endif
.dir = GPIO_INPUT,
.pull = GPIO_NO_PULL,
.enable = GPIO_ENABLE
},
{
+#if IS_ENABLED(CONFIG_IPQ_QFN_PART)
.gpio = 61,
.func = 2,
+#else /* bga */
+ .gpio = 17,
+ .func = 1,
+#endif
.dir = GPIO_OUTPUT,
.pull = GPIO_NO_PULL,
.enable = GPIO_ENABLE