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authorTaniya Das <tdas@codeaurora.org>2019-12-19 16:41:02 +0530
committerJulius Werner <jwerner@chromium.org>2020-02-07 23:12:00 +0000
commit91dc1e74a52ec33dc7f5c33dca73f02c5fe54cf0 (patch)
treed12a349c19549d7f1443fee76ba938a0dcccb416 /src/soc/qualcomm
parentbcd62f5737f5022b1bbe0041d4222575851b3cb9 (diff)
downloadcoreboot-91dc1e74a52ec33dc7f5c33dca73f02c5fe54cf0.tar.xz
sc7180: clock: Fix QUP DFSR configuration for perf levels
Update the QUP DFSR cmd to clear the SW control and also update the perf registers when M is set. While at it also update the d_2 values. Tested: validated DFSR clock configuration and M/N/D values. Change-Id: I6bba1c6f99810963aaa607885ef400c523c0e905 Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/qualcomm')
-rw-r--r--src/soc/qualcomm/sc7180/clock.c14
-rw-r--r--src/soc/qualcomm/sc7180/include/soc/clock.h1
2 files changed, 9 insertions, 6 deletions
diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c
index b447a54487..213c37ff3c 100644
--- a/src/soc/qualcomm/sc7180/clock.c
+++ b/src/soc/qualcomm/sc7180/clock.c
@@ -72,7 +72,7 @@ struct clock_config qup_wrap_cfg[] = {
.div = DIV(1),
.m = 8,
.n = 75,
- .d_2 = 150,
+ .d_2 = 75,
},
{
.hz = 48 * MHz,
@@ -80,7 +80,7 @@ struct clock_config qup_wrap_cfg[] = {
.div = DIV(1),
.m = 4,
.n = 25,
- .d_2 = 50,
+ .d_2 = 25,
},
{
.hz = 64 * MHz,
@@ -88,7 +88,7 @@ struct clock_config qup_wrap_cfg[] = {
.div = DIV(1),
.m = 16,
.n = 75,
- .d_2 = 150,
+ .d_2 = 75,
},
{
.hz = 96 * MHz,
@@ -96,7 +96,7 @@ struct clock_config qup_wrap_cfg[] = {
.div = DIV(1),
.m = 8,
.n = 25,
- .d_2 = 50,
+ .d_2 = 25,
},
{
.hz = 100 * MHz,
@@ -236,7 +236,9 @@ void clock_configure_dfsr(int qup)
struct sc7180_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ?
&gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s];
- setbits32(&qup_clk->dfsr_clk.cmd_dfsr, BIT(CLK_CTL_CMD_DFSR_SHFT));
+ clrsetbits32(&qup_clk->dfsr_clk.cmd_dfsr,
+ BIT(CLK_CTL_CMD_RCG_SW_CTL_SHFT),
+ BIT(CLK_CTL_CMD_DFSR_SHFT));
for (idx = 0; idx < ARRAY_SIZE(qup_wrap_cfg); idx++) {
reg_val = (qup_wrap_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) |
@@ -247,7 +249,7 @@ void clock_configure_dfsr(int qup)
if (qup_wrap_cfg[idx].m == 0)
continue;
- setbits32(&qup_clk->dfsr_clk.cmd_dfsr,
+ setbits32(&qup_clk->dfsr_clk.perf_dfsr[idx],
RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT);
reg_val = qup_wrap_cfg[idx].m & CLK_CTL_RCG_MND_BMSK;
diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h
index 2e44b60623..383e6d7be2 100644
--- a/src/soc/qualcomm/sc7180/include/soc/clock.h
+++ b/src/soc/qualcomm/sc7180/include/soc/clock.h
@@ -187,6 +187,7 @@ enum clk_ctl_bcr {
enum clk_ctl_dfsr {
CLK_CTL_CMD_DFSR_BMSK = 0x1,
CLK_CTL_CMD_DFSR_SHFT = 0,
+ CLK_CTL_CMD_RCG_SW_CTL_SHFT = 15,
};
enum clk_qup {