diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-23 17:25:58 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-01 11:44:51 +0000 |
| commit | 340e4b80904feb6c5c21497fc52966854fa5ee79 (patch) | |
| tree | 4026de0ec0cc41f51dd121a0be76642a8d0a286d /src/soc/qualcomm | |
| parent | 44874482fec69a849b06c378aa3eb69e75425256 (diff) | |
| download | coreboot-340e4b80904feb6c5c21497fc52966854fa5ee79.tar.xz | |
lib/cbmem_top: Add a common cbmem_top implementation
This adds a common cbmem_top implementation to all coreboot target.
In romstage a static variable will be used to cache the result of
cbmem_top_romstage.
In ramstage if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is set a global variable
needs to be populated by the stage entry with the value passed via the
calling arguments. if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is not set the
same implementation as will be used as in romstage.
Change-Id: Ie767542ee25483acc9a56785ce20a885e9a63098
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/qualcomm')
| -rw-r--r-- | src/soc/qualcomm/ipq40xx/cbmem.c | 2 | ||||
| -rw-r--r-- | src/soc/qualcomm/ipq806x/cbmem.c | 2 | ||||
| -rw-r--r-- | src/soc/qualcomm/qcs405/cbmem.c | 2 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7180/cbmem.c | 2 | ||||
| -rw-r--r-- | src/soc/qualcomm/sdm845/cbmem.c | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c index 05325cceb9..972c6258c9 100644 --- a/src/soc/qualcomm/ipq40xx/cbmem.c +++ b/src/soc/qualcomm/ipq40xx/cbmem.c @@ -23,7 +23,7 @@ void ipq_cbmem_backing_store_ready(void) cbmem_backing_store_ready = 1; } -void *cbmem_top(void) +void *cbmem_top_chipset(void) { /* * In romstage, make sure that cbmem backing store is ready before diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index 9674db65da..6dc92a0c11 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -23,7 +23,7 @@ void ipq_cbmem_backing_store_ready(void) cbmem_backing_store_ready = 1; } -void *cbmem_top(void) +void *cbmem_top_chipset(void) { /* * In romstage, make sure that cbmem backing store is ready before diff --git a/src/soc/qualcomm/qcs405/cbmem.c b/src/soc/qualcomm/qcs405/cbmem.c index e065409622..a780c6bcf1 100644 --- a/src/soc/qualcomm/qcs405/cbmem.c +++ b/src/soc/qualcomm/qcs405/cbmem.c @@ -15,7 +15,7 @@ #include <cbmem.h> -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return (void *)((uintptr_t)3 * GiB); } diff --git a/src/soc/qualcomm/sc7180/cbmem.c b/src/soc/qualcomm/sc7180/cbmem.c index 597e3692f8..fe81309c7a 100644 --- a/src/soc/qualcomm/sc7180/cbmem.c +++ b/src/soc/qualcomm/sc7180/cbmem.c @@ -15,7 +15,7 @@ #include <cbmem.h> -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return (void *)((uintptr_t)4 * GiB); } diff --git a/src/soc/qualcomm/sdm845/cbmem.c b/src/soc/qualcomm/sdm845/cbmem.c index 3b9ad4a617..b092a1a610 100644 --- a/src/soc/qualcomm/sdm845/cbmem.c +++ b/src/soc/qualcomm/sdm845/cbmem.c @@ -15,7 +15,7 @@ #include <cbmem.h> -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return (void *)((uintptr_t)4 * GiB); } |