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authorAkash Asthana <akashast@codeaurora.org>2019-06-24 11:28:34 +0530
committerJulius Werner <jwerner@chromium.org>2019-07-02 21:56:46 +0000
commit275f7ba5ac9b11a9dc044e5d344f27e6948008d2 (patch)
tree7d484d2f4c6c3f20b512581a9f473a48c96a9869 /src/soc/qualcomm
parentd19fa78ae73b3b76986ce65c71e254d7b7717cb5 (diff)
downloadcoreboot-275f7ba5ac9b11a9dc044e5d344f27e6948008d2.tar.xz
sdm845: Update macro definition in CB clock driver
Use literals KHz & MHz for kilohertz and megahertz frequency usages in macro definition. Change-Id: If1ca6e5e7b0603f93f3c980cc85af470fdcd54ba Signed-off-by: Akash Asthana <akashast@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/qualcomm')
-rw-r--r--src/soc/qualcomm/sdm845/include/soc/clock.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/qualcomm/sdm845/include/soc/clock.h b/src/soc/qualcomm/sdm845/include/soc/clock.h
index 6aee9c14f3..ea4d87d812 100644
--- a/src/soc/qualcomm/sdm845/include/soc/clock.h
+++ b/src/soc/qualcomm/sdm845/include/soc/clock.h
@@ -30,9 +30,9 @@
#define QUPV3_WRAP0_CLK_ENA_S(idx) (10 + idx)
#define QUPV3_WRAP1_CLK_ENA_S(idx) (22 + idx)
-#define GPLL0_EVEN_HZ (300*Mhz)
-#define GPLL0_MAIN_HZ (600*Mhz)
-#define QUP_WRAP_CORE_2X_19_2MHZ (19200*Khz)
+#define GPLL0_EVEN_HZ (300*MHz)
+#define GPLL0_MAIN_HZ (600*MHz)
+#define QUP_WRAP_CORE_2X_19_2MHZ (19200*KHz)
#define SRC_XO_19_2MHZ 0
#define SRC_GPLL0_MAIN_600MHZ 1