soc/rdc: Remove r8610 SoC

Bifferboard was the only board that used this chip, and it has now
been removed.  Removing the chip as well.  If there is desire to
continue work on the board, it can be found in the 4.6 branch.

Change-Id: I33a1e713cdfea47abce71b79f0a9c93562c96d12
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 0 insertions, 26 deletions

diff --git a/src/soc/rdc/r8610/bootblock.c b/src/soc/rdc/r8610/bootblock.c
deleted file mode 100644
index 0dc776ea93..0000000000
--- a/src/soc/rdc/r8610/bootblock.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <device/pci_def.h>
-
-static void bootblock_southbridge_init(void)
-{
-	uint32_t tmp;
-
-	tmp = pci_read_config32(PCI_DEV(0, 7, 0), 0x40);
-	/* decode all flash ranges */
-	pci_write_config32(PCI_DEV(0, 7, 0), 0x40, tmp | 0x07ff0000);
-}