diff options
author | Julius Werner <jwerner@chromium.org> | 2019-12-02 22:03:27 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-04 14:11:17 +0000 |
commit | 55009af42c39f413c49503670ce9bc2858974962 (patch) | |
tree | 099e9728bfe8066999de4d7a30021eb10bd71d12 /src/soc/rockchip/common/gpio.c | |
parent | 1c371572188a90ea16275460dd4ab6bf9966350b (diff) | |
download | coreboot-55009af42c39f413c49503670ce9bc2858974962.tar.xz |
Change all clrsetbits_leXX() to clrsetbitsXX()
This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.
This patch was created by running
sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'
across the codebase and cleaning up formatting a bit.
Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/rockchip/common/gpio.c')
-rw-r--r-- | src/soc/rockchip/common/gpio.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c index 3d7e1614e0..16ab385b03 100644 --- a/src/soc/rockchip/common/gpio.c +++ b/src/soc/rockchip/common/gpio.c @@ -24,16 +24,16 @@ static void gpio_set_dir(gpio_t gpio, enum gpio_dir dir) { - clrsetbits_le32(&gpio_port[gpio.port]->swporta_ddr, - 1 << gpio.num, dir << gpio.num); + clrsetbits32(&gpio_port[gpio.port]->swporta_ddr, + 1 << gpio.num, dir << gpio.num); } static void gpio_set_pull(gpio_t gpio, enum gpio_pull pull) { u32 pull_val = gpio_get_pull_val(gpio, pull); if (is_pmu_gpio(gpio) && CONFIG(SOC_ROCKCHIP_RK3288)) - clrsetbits_le32(gpio_grf_reg(gpio), 3 << (gpio.idx * 2), - pull_val << (gpio.idx * 2)); + clrsetbits32(gpio_grf_reg(gpio), 3 << (gpio.idx * 2), + pull_val << (gpio.idx * 2)); else write32(gpio_grf_reg(gpio), RK_CLRSETBITS(3 << (gpio.idx * 2), pull_val << (gpio.idx * 2))); @@ -83,13 +83,13 @@ void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, enum gpio_pull pull) case IRQ_TYPE_LEVEL_LOW: break; } - clrsetbits_le32(&gpio_port[gpio.port]->int_polarity, - mask, int_polarity); - clrsetbits_le32(&gpio_port[gpio.port]->inttype_level, - mask, inttype_level); + clrsetbits32(&gpio_port[gpio.port]->int_polarity, + mask, int_polarity); + clrsetbits32(&gpio_port[gpio.port]->inttype_level, + mask, inttype_level); - setbits_le32(&gpio_port[gpio.port]->inten, mask); - clrbits_le32(&gpio_port[gpio.port]->intmask, mask); + setbits32(&gpio_port[gpio.port]->inten, mask); + clrbits32(&gpio_port[gpio.port]->intmask, mask); } int gpio_irq_status(gpio_t gpio) @@ -100,7 +100,7 @@ int gpio_irq_status(gpio_t gpio) if (!(int_status & mask)) return 0; - setbits_le32(&gpio_port[gpio.port]->porta_eoi, mask); + setbits32(&gpio_port[gpio.port]->porta_eoi, mask); return 1; } @@ -111,8 +111,8 @@ int gpio_get(gpio_t gpio) void gpio_set(gpio_t gpio, int value) { - clrsetbits_le32(&gpio_port[gpio.port]->swporta_dr, 1 << gpio.num, - !!value << gpio.num); + clrsetbits32(&gpio_port[gpio.port]->swporta_dr, 1 << gpio.num, + !!value << gpio.num); } void gpio_output(gpio_t gpio, int value) |