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authorJulius Werner <jwerner@chromium.org>2019-05-01 16:51:20 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-05-06 10:32:15 +0000
commit7c712bbb6c969ae7014707bfddedd821035a2171 (patch)
tree4c357814eabac828a5d7cea3e0bd90b5b15851d1 /src/soc/rockchip/common
parent9d3fa7a22985a2ae080a8e36c89107691d15174f (diff)
downloadcoreboot-7c712bbb6c969ae7014707bfddedd821035a2171.tar.xz
Fix code that would trip -Wtype-limits
This patch fixes up all code that would throw a -Wtype-limits warning. This sometimes involves eliminating unnecessary checks, adding a few odd but harmless casts or just pragma'ing out the warning for a whole file -- I tried to find the path of least resistance. I think the overall benefit of the warning outweighs the occasional weirdness. Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32537 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/rockchip/common')
-rw-r--r--src/soc/rockchip/common/spi.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c
index 98016c0fc9..e929419a14 100644
--- a/src/soc/rockchip/common/spi.c
+++ b/src/soc/rockchip/common/spi.c
@@ -96,7 +96,7 @@ static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz)
void rockchip_spi_init(unsigned int bus, unsigned int speed_hz)
{
- assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves));
+ assert(bus < ARRAY_SIZE(rockchip_spi_slaves));
struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs;
unsigned int ctrlr0 = 0;
@@ -134,13 +134,13 @@ void rockchip_spi_init(unsigned int bus, unsigned int speed_hz)
void rockchip_spi_set_sample_delay(unsigned int bus, unsigned int delay_ns)
{
- assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves));
+ assert(bus < ARRAY_SIZE(rockchip_spi_slaves));
struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs;
unsigned int rsd;
/* Rxd Sample Delay */
rsd = DIV_ROUND_CLOSEST(delay_ns * (SPI_SRCCLK_HZ >> 8), 1*GHz >> 8);
- assert(rsd >= 0 && rsd <= 3);
+ assert(rsd <= 3);
clrsetbits_le32(&regs->ctrlr0, SPI_RXDSD_MASK << SPI_RXDSD_OFFSET,
rsd << SPI_RXDSD_OFFSET);
}