diff options
| author | Lin Huang <hl@rock-chips.com> | 2016-10-23 14:17:25 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-14 18:08:11 +0100 |
| commit | a09b338362c09aebf5f35a63b2412f358621db0f (patch) | |
| tree | 5d87706ae5209bd0507ed27e9b8fbf8405e01bca /src/soc/rockchip/common | |
| parent | 1d6957e9a99e1cdfc50a2b60a8d67b4809604216 (diff) | |
| download | coreboot-a09b338362c09aebf5f35a63b2412f358621db0f.tar.xz | |
soc/rockchip: split edp_enable() function
To avoid garbage display in firmware on warm reset, we need
to enable eDP display in depthcharge instead when the framebuffer is
cleared.
Therefore limit edp_enable() in coreboot to just configure eDP,
and leave enabling the display to depthcharge.
CQ-DEPEND=CL:402071
BUG=chrome-os-partner:58675
BRANCH=none
TEST=Boot from kevin, and display work
Change-Id: I9d937ead33ebba58e33e02fd73b80d6e11bb69aa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 38b0d18c3fae37dfccb18fe809f763b98703167c
Original-Change-Id: Ibbc283a5892b98f4922f02fd67465fe2e1d01b71
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/402095
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17207
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/rockchip/common')
| -rw-r--r-- | src/soc/rockchip/common/edp.c | 15 | ||||
| -rw-r--r-- | src/soc/rockchip/common/include/soc/edp.h | 1 |
2 files changed, 11 insertions, 5 deletions
diff --git a/src/soc/rockchip/common/edp.c b/src/soc/rockchip/common/edp.c index 90bc6e7a33..5723ccf660 100644 --- a/src/soc/rockchip/common/edp.c +++ b/src/soc/rockchip/common/edp.c @@ -921,10 +921,7 @@ static int rk_edp_config_video(struct rk_edp *edp) /* Disable video mute */ clrbits_le32(&edp->regs->video_ctl_1, VIDEO_MUTE); - /* Enable video at next frame */ - setbits_le32(&edp->regs->video_ctl_1, VIDEO_EN); - - return rk_edp_is_video_stream_on(edp); + return 0; } static void rockchip_edp_force_hpd(struct rk_edp *edp) @@ -985,7 +982,7 @@ int rk_edp_get_edid(struct edid *edid) return retval; } -int rk_edp_enable(void) +int rk_edp_prepare(void) { int ret = 0; @@ -1002,6 +999,14 @@ int rk_edp_enable(void) return ret; } +int rk_edp_enable(void) +{ + /* Enable video at next frame */ + setbits_le32(&rk_edp.regs->video_ctl_1, VIDEO_EN); + + return rk_edp_is_video_stream_on(&rk_edp); +} + void rk_edp_init(void) { rk_edp.regs = (struct rk_edp_regs *)EDP_BASE; diff --git a/src/soc/rockchip/common/include/soc/edp.h b/src/soc/rockchip/common/include/soc/edp.h index 1721fc0226..a9ebbc5089 100644 --- a/src/soc/rockchip/common/include/soc/edp.h +++ b/src/soc/rockchip/common/include/soc/edp.h @@ -651,6 +651,7 @@ struct rk_edp { u8 train_set[4]; }; +int rk_edp_prepare(void); int rk_edp_enable(void); void rk_edp_init(void); int rk_edp_get_edid(struct edid *edid); |