diff options
author | jinkun.hong <jinkun.hong@rock-chips.com> | 2014-06-22 20:40:39 -0700 |
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committer | Marc Jones <marc.jones@se-eng.com> | 2015-03-16 04:52:46 +0100 |
commit | ac490b8a6bb31bf39fe8087ac3ba6a9b814beb87 (patch) | |
tree | 46a12e4bdf7cb7a82518ee09e70306701330124f /src/soc/rockchip/rk3288/Kconfig | |
parent | a74d569731ab19a81a1c125b9d65659408649265 (diff) | |
download | coreboot-ac490b8a6bb31bf39fe8087ac3ba6a9b814beb87.tar.xz |
coreboot: rk3288: Add a stub implementation of the rk3288 SOC
Most things still needs to be filled in, but this will allow us to build boards which use this SOC.
BUG=chrome-os-partner:29778
TEST=emerge-veyron coreboot
Original-Change-Id: If643d620c5fb8951faaf1ccde400a8e9ed7db3bc
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205069
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 2f72473a8c2b3fe21d77b351338e6209035878fb)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I53fd0ced42f6ef191d7bf80d8b823bb880344239
Reviewed-on: http://review.coreboot.org/8653
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/rockchip/rk3288/Kconfig')
-rw-r--r-- | src/soc/rockchip/rk3288/Kconfig | 118 |
1 files changed, 118 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig new file mode 100644 index 0000000000..51cf74ca65 --- /dev/null +++ b/src/soc/rockchip/rk3288/Kconfig @@ -0,0 +1,118 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOC_ROCKCHIP_RK3288 + bool + default n + select ARCH_BOOTBLOCK_ARMV7 + select ARCH_VERSTAGE_ARMV7 + select ARCH_ROMSTAGE_ARMV7 + select ARCH_RAMSTAGE_ARMV7 + select CPU_HAS_BOOTBLOCK_INIT + select HAVE_MONOTONIC_TIMER + select HAVE_UART_MEMORY_MAPPED + select HAVE_UART_SPECIAL + select BOOTBLOCK_CONSOLE + select DYNAMIC_CBMEM + +if SOC_ROCKCHIP_RK3288 + +config BOOTBLOCK_CPU_INIT + string + default "soc/rockchip/rk3288/bootblock.c" + +# ROM image layout. +# +# 0x00000 Combined bootblock and ID Block +# 0x08000 Master CBFS header. +# 0x18000 Free for CBFS data. +# +# iRAM (96k) layout. +# (Note: The BootROM will jump to 0xff704004 after loading bootblock, +# so the bootblock loading address must be at 0xff704004.) +# +# 0xFF70_0000 TTB (16KB). +# 0xFF70_4004 Bootblock (max 16KB-4B). +# 0xFF70_8000 ROM stage (max 40KB). +# 0xFF71_2000 STACK (4KB). +# 0xFF71_3000 CBFS mapping cache (20K) +# 0xFF71_7FFF End of iRAM. + +config SYS_SDRAM_BASE + hex "SDRAM base address" + default 0x00000000 + +config STACK_TOP + hex "STACK TOP" + default 0xff713000 + +config STACK_BOTTOM + hex "STACK BOTTOM" + default 0xff712000 + +config BOOTBLOCK_BASE + hex + default 0xff704004 + +config ROMSTAGE_BASE + hex "ROM STAGE BASE" + default 0xff708000 + +config RAMSTAGE_BASE + hex "RAMSTAGE BASE" + default 0x00200000 + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x0 + +config CBFS_HEADER_ROM_OFFSET + hex + default 0x0008000 + +config CBFS_ROM_OFFSET + hex + default 0x0018000 + +config CBFS_SRAM_CACHE_ADDRESS + hex "sram memory address to put CBFS cache data" + default 0xff713000 + +config CBFS_SRAM_CACHE_SIZE + hex "size of CBFS cache data" + default 0x00005000 + +config CBFS_DRAM_CACHE_ADDRESS + hex "dram memory address to put CBFS cache data" + default 0x01000000 + +config CBFS_DRAM_CACHE_SIZE + hex "size of CBFS cache data" + default 0x00100000 + +config TTB_BUFFER + hex "memory address of the TTB buffer" + default 0xff700000 + +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on CONSOLE_SERIAL_UART + default 0xFF690000 + +endif |