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| author | Jinkun Hong <jinkun.hong@rock-chips.com> | 2014-08-28 09:37:22 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-24 15:25:23 +0100 |
| commit | c33ce3554ddc73635084e6e71b5e4f7dae021926 (patch) | |
| tree | c727bcdeb697d2dde1ba983a1af08a07083c4b2f /src/soc/rockchip/rk3288/Makefile.inc | |
| parent | d5fb66e060954f8505cfceed371aace9c8285fe7 (diff) | |
| download | coreboot-c33ce3554ddc73635084e6e71b5e4f7dae021926.tar.xz | |
rk3288: add ddr driver
Supports DDR3 and LPDDR3.Supports dual channel.ddr max freq is 533mhz.
ddr timing config file in src\mainboard\google\veyron\sdram_inf
Remove dpll init in rk clk_init(), add rkclk_configure_ddr(unsigned int hz).
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: I429eb0b8c365c6285fb6cfef008b41776cc9c2d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 52838c68fe6963285c974af5dc5837e819efc321
Original-Change-Id: I6ddfe30b8585002b45060fe998c9238cbb611c05
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209465
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8865
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/rockchip/rk3288/Makefile.inc')
| -rw-r--r-- | src/soc/rockchip/rk3288/Makefile.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index 4818cafb11..446aa7842d 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -39,7 +39,7 @@ romstage-y += clock.c romstage-y += gpio.c romstage-y += spi.c romstage-y += media.c - +romstage-y += sdram.c ramstage-y += cbmem.c ramstage-y += timer.c |