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authorhuang lin <hl@rock-chips.com>2014-09-27 12:02:27 +0800
committerAaron Durbin <adurbin@google.com>2015-04-02 21:16:28 +0200
commitbbcffd9e25e12a8ee5858ac580aa7e86ecf32ee5 (patch)
tree71643c01f781877ae677f424dbfb6023f521e4d7 /src/soc/rockchip/rk3288/bootblock.c
parent1fd5a9b36d8b817614ef7f0c301291da0cdb7466 (diff)
downloadcoreboot-bbcffd9e25e12a8ee5858ac580aa7e86ecf32ee5.tar.xz
rockchip: support i2c clock setting
BUG=None TEST=Boot Veyron Pinky and measure i2c clock frequency Original-Change-Id: I04d9fa75a05280885f083a828f78cf55811ca97d Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219660 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Change-Id: Ie7ac3f2d0d76a4d3347bd469bf7af3295cc454fd (cherry picked from commit 4b9b3c2f8b7c6cd189cb8f239508431ee08ebc52) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9241 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/rockchip/rk3288/bootblock.c')
-rw-r--r--src/soc/rockchip/rk3288/bootblock.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c
index 635eee45b3..d7bc67a38d 100644
--- a/src/soc/rockchip/rk3288/bootblock.c
+++ b/src/soc/rockchip/rk3288/bootblock.c
@@ -26,6 +26,7 @@
#include "grf.h"
#include "spi.h"
#include <vendorcode/google/chromeos/chromeos.h>
+#include <soc/rockchip/rk3288/i2c.h>
static void bootblock_cpu_init(void)
{
@@ -34,11 +35,15 @@ static void bootblock_cpu_init(void)
writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
/*i2c1 for tpm*/
writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
+
/* spi0 for chrome ec */
writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
rk3288_init_timer();
console_init();
rkclk_init();
+
+ /*i2c1 for tpm 400khz*/
+ i2c_init(1, 400000);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
setup_chromeos_gpios();