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| author | huang lin <hl@rock-chips.com> | 2014-12-09 09:49:21 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-15 07:33:27 +0200 |
| commit | 5984aad9c8a0fad5b20db7d03832d3b3510bcfd6 (patch) | |
| tree | 1e026dc2803d1099f1b384c5a5d1054d4a053b65 /src/soc/rockchip/rk3288/clock.c | |
| parent | 346ea77c9da3701adbb7857de6f188d3b1d398fb (diff) | |
| download | coreboot-5984aad9c8a0fad5b20db7d03832d3b3510bcfd6.tar.xz | |
veyron_speedy: Support Samsung-4GB and Lynix-4GB LPDDR
Add the Samsung-4GB and Hynix-4GB LPDDR inc files.
Use ram_id 1000 correspond to Samsung-4GB LPDDR
and use ram_id 1001 correspond to Hynix-4GB LPDDR.
BUG=chrome-os-partner:33269
TEST=Boot veyron_speedy normal
BRANCH=None
Change-Id: I21983c48e1e99aa70ae9bb3fb6550ae9af472015
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: d34b19dc9b57b4f31dc1b28581f3f8fc0fcc7e6b
Original-Change-Id: I55b6968c642df8c1f579e518232ab5d278e7e12f
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/233859
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9628
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/soc/rockchip/rk3288/clock.c')
0 files changed, 0 insertions, 0 deletions