diff options
| author | Julius Werner <jwerner@chromium.org> | 2014-10-06 13:41:28 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2015-04-04 15:02:24 +0200 |
| commit | b6092b7e396d5e7ab55cb7c11375b6a8fec7cd61 (patch) | |
| tree | 56d05fa074c4df23708fe05a6f1dc87b69c67daf /src/soc/rockchip/rk3288/clock.c | |
| parent | 46826c36bf1af1dcb4535f0838933f01f600a9d7 (diff) | |
| download | coreboot-b6092b7e396d5e7ab55cb7c11375b6a8fec7cd61.tar.xz | |
veyron_pinky/rk3288: Use KHz, MHz and GHz constants
Use the previously added frequency constants in patch
titled 'stddef: Add KHz, MHz and GHz constants'.
BUG=None
TEST=Compiled Veyron_Pinky.
Original-Change-Id: I4a1927fd423eb96d3f76f7e44b451192038b02e0
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/221800
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 41bb8026818b4381d4a6d43d2d433c207c3971bc)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I37a610d57f1a3d44796bf80de5104c2b5b3f3dac
Reviewed-on: http://review.coreboot.org/9254
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/rockchip/rk3288/clock.c')
| -rw-r--r-- | src/soc/rockchip/rk3288/clock.c | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 8202ef2127..0ce3f9450a 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -65,8 +65,8 @@ check_member(rk3288_cru_reg, cru_emmc_con[1], 0x021c); static struct rk3288_cru_reg * const cru_ptr = (void *)CRU_BASE; #define PLL_DIVISORS(hz, _nr, _no) {\ - .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / 24000000), .no = _no};\ - _Static_assert(((u64)hz * _nr * _no / 24000000) * 24000000 /\ + .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / (24*MHz)), .no = _no};\ + _Static_assert(((u64)hz * _nr * _no / (24*MHz)) * (24*MHz) /\ (_nr * _no) == hz,\ #hz "Hz cannot be hit with PLL divisors in " __FILE__); @@ -337,10 +337,10 @@ void rkclk_configure_ddr(unsigned int hz) { struct pll_div dpll_cfg; - if (hz <= 150000000) { + if (hz <= 150*MHz) { dpll_cfg.nr = 3; dpll_cfg.no = 8; - } else if (hz <= 540000000) { + } else if (hz <= 540*MHz) { dpll_cfg.nr = 6; dpll_cfg.no = 4; } else { @@ -348,10 +348,9 @@ void rkclk_configure_ddr(unsigned int hz) dpll_cfg.no = 1; } - dpll_cfg.nf = (hz / 1000 * dpll_cfg.nr * dpll_cfg.no) / 24000; - assert(dpll_cfg.nf < 4096 - && hz == dpll_cfg.nf * 24000 / (dpll_cfg.nr * dpll_cfg.no) - * 1000); + dpll_cfg.nf = (hz/KHz * dpll_cfg.nr * dpll_cfg.no) / (24*KHz); + assert(dpll_cfg.nf < 4096 && hz == dpll_cfg.nf * (24*KHz) / + (dpll_cfg.nr * dpll_cfg.no) * 1000); /* pll enter slow-mode */ writel(RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_SLOW), &cru_ptr->cru_mode_con); |