diff options
author | huang lin <hl@rock-chips.com> | 2014-08-27 17:07:42 +0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-24 15:25:31 +0100 |
commit | 739df1b2c2e334dfd03b81393cf1e95f0cb98607 (patch) | |
tree | 42306d8213012b947274ce54e1040b784bb8a728 /src/soc/rockchip/rk3288/clock.c | |
parent | 82ba4d092b729d0063a22d445f315d08ad7a3e07 (diff) | |
download | coreboot-739df1b2c2e334dfd03b81393cf1e95f0cb98607.tar.xz |
rk3288: update romstage & mainboard
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: I877b4bf741f45f6cfd032ad5018a60e8a1453622
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 640da5ad5597803c62d9374a1a48832003077723
Original-Change-Id: I805d93e94f73418099f47d235ca920a91b4b2bfb
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209469
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8867
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/rockchip/rk3288/clock.c')
-rwxr-xr-x | src/soc/rockchip/rk3288/clock.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index d2ef0aa6d2..6d6262884a 100755 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -339,3 +339,34 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz) printk(BIOS_ERR, "do not support this spi bus\n"); } } + +static u32 clk_gcd(u32 a, u32 b) +{ + while (b != 0) { + int r = b; + b = a % b; + a = r; + } + return a; +} + +void rkclk_configure_i2s(unsigned int hz) +{ + int n, d; + int v; + + /* i2s source clock: gpll + i2s0_outclk_sel: clk_i2s + i2s0_clk_sel: divider ouput from fraction + i2s0_pll_div_con: 0*/ + writel(RK_CLRSETBITS(1 << 15 | 1 << 12 | 3 << 8 | 0x7f << 0 , + 1 << 15 | 0 << 12 | 1 << 8 | 0 << 0), + &cru_ptr->cru_clksel_con[4]); + + /* set frac divider */ + v = clk_gcd(GPLL_HZ, hz); + n = (GPLL_HZ / v) & (0xffff); + d = (hz / v) & (0xffff); + assert(hz == GPLL_HZ / n * d); + writel(d << 16 | n, &cru_ptr->cru_clksel_con[8]); +} |