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authorLin Huang <hl@rock-chips.com>2016-04-25 18:50:55 +0800
committerPatrick Georgi <pgeorgi@google.com>2016-05-09 08:48:35 +0200
commitb9a7877568cf7441cef7879c9948c8c3a8895a60 (patch)
tree89e4b35fce0fd7c1e8129e751a577facaad82c80 /src/soc/rockchip/rk3288/display.c
parentf9cbe353193a506fb687f137ddd7b082b0da5a49 (diff)
downloadcoreboot-b9a7877568cf7441cef7879c9948c8c3a8895a60.tar.xz
rockchip/*: refactor edp driver
rk3288 and rk3399 use same edp IP, move soc specific setting to soc/display, and move edp driver to common, so rk3399 can reuse this driver. BUG=chrome-os-partner:52460 BRANCH=none TEST= test on jerry and mighty, edp panel can work Change-Id: Ie3f3e8468b2323994af8a002413bf93b3edc8026 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64bb4b2c7ed373d9730c9aa0b0896a32164fc7ee Original-Change-Id: Ie5c15a81849a02d1c0457e36ed00fbe2d47961fb Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/340504 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14725 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/rockchip/rk3288/display.c')
-rw-r--r--src/soc/rockchip/rk3288/display.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c
index 306baad3b6..f3dfac1a86 100644
--- a/src/soc/rockchip/rk3288/display.c
+++ b/src/soc/rockchip/rk3288/display.c
@@ -39,6 +39,7 @@ void rk_display_init(device_t dev, u32 lcdbase,
unsigned long fb_size)
{
struct edid edid;
+ uint32_t val;
struct soc_rockchip_rk3288_config *conf = dev->chip_info;
uint32_t lower = ALIGN_DOWN(lcdbase, MiB);
uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB);
@@ -58,7 +59,16 @@ void rk_display_init(device_t dev, u32 lcdbase,
printk(BIOS_DEBUG, "Attempting to setup EDP display.\n");
rkclk_configure_edp();
rkclk_configure_vop_aclk(conf->vop_id, 192 * MHz);
- rk_edp_init(conf->vop_id);
+
+ /* grf_edp_ref_clk_sel: from internal 24MHz or 27MHz clock */
+ write32(&rk3288_grf->soc_con12, RK_SETBITS(1 << 4));
+
+ /* select epd signal from vop0 or vop1 */
+ val = (conf->vop_id == 1) ? RK_SETBITS(1 << 5) :
+ RK_CLRBITS(1 << 5);
+ write32(&rk3288_grf->soc_con6, val);
+
+ rk_edp_init();
if (rk_edp_get_edid(&edid) == 0) {
detected_mode = VOP_MODE_EDP;