rockchip: refactor gpio driver

The gpio of rockchip SoCs(rk3288 & rk3399) are the same IP,
moving the gpio code of rk3288 to common then can be reused on rk3399.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=build and boot into chromeos on veyron_jerry

Change-Id: I10a4b9d32afe60fd52512f2ad0007e9d2785033b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1c0c4b4b999790b0be7b0eeb70d2a7a86158f779
Original-Change-Id: If13b7760108831d81e8e8c950cdf61724d497b17
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/339846
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14712
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 19 insertions, 48 deletions

diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c
index 35b4b7ee88..8a15b85908 100644
--- a/src/soc/rockchip/rk3288/gpio.c
+++ b/src/soc/rockchip/rk3288/gpio.c
@@ -16,66 +16,37 @@
 #include <arch/io.h>
 #include <console/console.h>
 #include <gpio.h>
+#include <soc/gpio.h>
 #include <soc/grf.h>
 #include <soc/pmu.h>
 #include <soc/soc.h>
 #include <stdlib.h>
 
-struct rk3288_gpio_regs *gpio_port[] = {
-	(struct rk3288_gpio_regs *)0xff750000,
-	(struct rk3288_gpio_regs *)0xff780000,
-	(struct rk3288_gpio_regs *)0xff790000,
-	(struct rk3288_gpio_regs *)0xff7a0000,
-	(struct rk3288_gpio_regs *)0xff7b0000,
-	(struct rk3288_gpio_regs *)0xff7c0000,
-	(struct rk3288_gpio_regs *)0xff7d0000,
-	(struct rk3288_gpio_regs *)0xff7e0000,
-	(struct rk3288_gpio_regs *)0xff7f0000
-};
-
-enum {
-	PULLNONE = 0,
-	PULLUP,
-	PULLDOWN
+struct rockchip_gpio_regs *gpio_port[] = {
+	(struct rockchip_gpio_regs *)0xff750000,
+	(struct rockchip_gpio_regs *)0xff780000,
+	(struct rockchip_gpio_regs *)0xff790000,
+	(struct rockchip_gpio_regs *)0xff7a0000,
+	(struct rockchip_gpio_regs *)0xff7b0000,
+	(struct rockchip_gpio_regs *)0xff7c0000,
+	(struct rockchip_gpio_regs *)0xff7d0000,
+	(struct rockchip_gpio_regs *)0xff7e0000,
+	(struct rockchip_gpio_regs *)0xff7f0000
 };
 
 #define PMU_GPIO_PORT 0
 
-static void __gpio_input(gpio_t gpio, u32 pull)
+int is_pmu_gpio(gpio_t gpio)
 {
-	clrbits_le32(&gpio_port[gpio.port]->swporta_ddr, 1 << gpio.num);
 	if (gpio.port == PMU_GPIO_PORT)
-		clrsetbits_le32(&rk3288_pmu->gpio0pull[gpio.bank],
-				3 << (gpio.idx * 2),  pull << (gpio.idx * 2));
-	else
-		write32(&rk3288_grf->gpio1_p[(gpio.port - 1)][gpio.bank],
-			RK_CLRSETBITS(3 << (gpio.idx * 2),
-				   pull << (gpio.idx * 2)));
-}
-
-void gpio_input(gpio_t gpio)
-{
-	__gpio_input(gpio, PULLNONE);
-}
-
-void gpio_input_pulldown(gpio_t gpio)
-{
-	__gpio_input(gpio, PULLDOWN);
-}
-
-void gpio_input_pullup(gpio_t gpio)
-{
-	__gpio_input(gpio, PULLUP);
-}
-
-int gpio_get(gpio_t gpio)
-{
-	return (read32(&gpio_port[gpio.port]->ext_porta) >> gpio.num) & 0x1;
+		return 1;
+	return 0;
 }
 
-void gpio_output(gpio_t gpio, int value)
+void *gpio_grf_reg(gpio_t gpio)
 {
-	setbits_le32(&gpio_port[gpio.port]->swporta_ddr, 1 << gpio.num);
-	clrsetbits_le32(&gpio_port[gpio.port]->swporta_dr, 1 << gpio.num,
-							   !!value << gpio.num);
+	if (is_pmu_gpio(gpio))
+		return &rk3288_pmu->gpio0pull[gpio.bank];
+	/* There is one pmu gpio, gpio0 , so " - 1" */
+	return &rk3288_grf->gpio1_p[(gpio.port - 1)][gpio.bank];
 }