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authorJulius Werner <jwerner@chromium.org>2015-02-19 14:51:15 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-21 08:22:28 +0200
commit2f37bd65518865688b9234afce0d467508d6f465 (patch)
treeeba5ed799de966299602b30c70d51dd40eaadd73 /src/soc/rockchip/rk3288/pwm.c
parent1f60f971fc89ef841e81b978964b38278d597b1d (diff)
downloadcoreboot-2f37bd65518865688b9234afce0d467508d6f465.tar.xz
arm(64): Globally replace writel(v, a) with write32(a, v)
This patch is a raw application of the following spatch to src/: @@ expression A, V; @@ - writel(V, A) + write32(A, V) @@ expression A, V; @@ - writew(V, A) + write16(A, V) @@ expression A, V; @@ - writeb(V, A) + write8(A, V) @@ expression A; @@ - readl(A) + read32(A) @@ expression A; @@ - readb(A) + read8(A) BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6 Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254864 Reviewed-on: http://review.coreboot.org/9836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/rockchip/rk3288/pwm.c')
-rw-r--r--src/soc/rockchip/rk3288/pwm.c12
1 files changed, 5 insertions, 7 deletions
diff --git a/src/soc/rockchip/rk3288/pwm.c b/src/soc/rockchip/rk3288/pwm.c
index a44724959e..fb47dc8312 100644
--- a/src/soc/rockchip/rk3288/pwm.c
+++ b/src/soc/rockchip/rk3288/pwm.c
@@ -73,17 +73,15 @@ void pwm_init(u32 id, u32 period_ns, u32 duty_ns)
unsigned long period, duty;
/*use rk pwm*/
- writel(RK_SETBITS(1 << 0), &rk3288_grf->soc_con2);
+ write32(&rk3288_grf->soc_con2, RK_SETBITS(1 << 0));
- writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE |
- PWM_CONTINUOUS | PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE |
- RK_PWM_DISABLE,
- &rk3288_pwm->pwm[id].pwm_ctrl);
+ write32(&rk3288_pwm->pwm[id].pwm_ctrl,
+ PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_CONTINUOUS | PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE | RK_PWM_DISABLE);
period = (PD_BUS_PCLK_HZ / 1000) * period_ns / USECS_PER_SEC;
duty = (PD_BUS_PCLK_HZ / 1000) * duty_ns / USECS_PER_SEC;
- writel(period, &rk3288_pwm->pwm[id].pwm_period_hpr);
- writel(duty, &rk3288_pwm->pwm[id].pwm_duty_lpr);
+ write32(&rk3288_pwm->pwm[id].pwm_period_hpr, period);
+ write32(&rk3288_pwm->pwm[id].pwm_duty_lpr, duty);
setbits_le32(&rk3288_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE);
}