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| author | Yakir Yang <ykk@rock-chips.com> | 2015-07-27 08:50:36 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-08-28 06:43:32 +0000 |
| commit | 8c3ab6a5f1e36ddf2c22abacee47afaddd7d0bb8 (patch) | |
| tree | 74183d2a00f0e0722373044ff3ee0acc3a4788ec /src/soc/rockchip/rk3288/pwm.c | |
| parent | 9a640597e698af45558be8bb7aaab6c3b6f28d39 (diff) | |
| download | coreboot-8c3ab6a5f1e36ddf2c22abacee47afaddd7d0bb8.tar.xz | |
rockchip: rk3288: multiple NPLL rate in pll_para_config
Due to HDMI need to set dclk_rate to 27Mhz, and we can't
caclu a suitable config paramters for this rate, so we
need to multiple rate unless the vco larger then VCO_MAX.
When NPLL rate multiple to 54MHz, pll_para_config could
caclu a right paramters, and I have verify the clock jitter
is okay to HDMI output.
Jitter Reports:
Dclk Rate NPLL Rate nr/no/nf jitter Margin
27MHz 54MHz 2/10/45 449.0ps +51.0%
BRANCH=None
BUG=chrome-os-partner:42946
TEST=Mickey board, show right recovery picture on TV,
and 480p clock jitter test passed
Change-Id: Iaa0a6622e63d88918ed465900e630bdf16fde706
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 59f1552026889f61167cfeaec3def668ba709c10
Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Original-Change-Id: Iab274b41f163d2d61332df13e5091f0b605cb65c
Original-Reviewed-on: https://chromium-review.googlesource.com/288416
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290331
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/11393
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/rockchip/rk3288/pwm.c')
0 files changed, 0 insertions, 0 deletions