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authorJulius Werner <jwerner@chromium.org>2014-10-06 13:41:28 -0700
committerAaron Durbin <adurbin@google.com>2015-04-04 15:02:24 +0200
commitb6092b7e396d5e7ab55cb7c11375b6a8fec7cd61 (patch)
tree56d05fa074c4df23708fe05a6f1dc87b69c67daf /src/soc/rockchip/rk3288/sdram.c
parent46826c36bf1af1dcb4535f0838933f01f600a9d7 (diff)
downloadcoreboot-b6092b7e396d5e7ab55cb7c11375b6a8fec7cd61.tar.xz
veyron_pinky/rk3288: Use KHz, MHz and GHz constants
Use the previously added frequency constants in patch titled 'stddef: Add KHz, MHz and GHz constants'. BUG=None TEST=Compiled Veyron_Pinky. Original-Change-Id: I4a1927fd423eb96d3f76f7e44b451192038b02e0 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221800 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 41bb8026818b4381d4a6d43d2d433c207c3971bc) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I37a610d57f1a3d44796bf80de5104c2b5b3f3dac Reviewed-on: http://review.coreboot.org/9254 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/rockchip/rk3288/sdram.c')
-rw-r--r--src/soc/rockchip/rk3288/sdram.c32
1 files changed, 16 insertions, 16 deletions
diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c
index 6c0c7fd136..2b0a396bb7 100644
--- a/src/soc/rockchip/rk3288/sdram.c
+++ b/src/soc/rockchip/rk3288/sdram.c
@@ -538,8 +538,8 @@ static void phy_dll_bypass_set(struct rk3288_ddr_publ_regs *ddr_publ_regs,
u32 freq)
{
int i;
- if (freq <= 250000000) {
- if (freq <= 150000000)
+ if (freq <= 250*MHz) {
+ if (freq <= 150*MHz)
clrbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS);
else
setbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS);
@@ -651,19 +651,19 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params)
writel(sdram_params->noc_activate, &msch_regs->activate);
writel(BUSWRTORD(2) | BUSRDTOWR(2) | BUSRDTORD(1),
&msch_regs->devtodev);
- writel(PRT_DLLLOCK(div_round_up(sdram_params->ddr_freq / 1000000
- * 5120, 1000))
- | PRT_DLLSRST(div_round_up(sdram_params->ddr_freq / 1000000
- * 50, 1000))
+ writel(PRT_DLLLOCK(div_round_up(sdram_params->ddr_freq/MHz
+ * 5120, 1000))
+ | PRT_DLLSRST(div_round_up(sdram_params->ddr_freq/MHz
+ * 50, 1000))
| PRT_ITMSRST(8), &ddr_publ_regs->ptr[0]);
- writel(PRT_DINIT0(div_round_up(sdram_params->ddr_freq / 1000000
- * 500000, 1000))
- | PRT_DINIT1(div_round_up(sdram_params->ddr_freq / 1000000
- * 400, 1000)), &ddr_publ_regs->ptr[1]);
- writel(PRT_DINIT2(div_round_up(sdram_params->ddr_freq / 1000000
- * 200000, 1000))
- | PRT_DINIT3(div_round_up(sdram_params->ddr_freq / 1000000
- * 1000, 1000)), &ddr_publ_regs->ptr[2]);
+ writel(PRT_DINIT0(div_round_up(sdram_params->ddr_freq/MHz
+ * 500000, 1000))
+ | PRT_DINIT1(div_round_up(sdram_params->ddr_freq/MHz
+ * 400, 1000)), &ddr_publ_regs->ptr[1]);
+ writel(PRT_DINIT2(div_round_up(sdram_params->ddr_freq/MHz
+ * 200000, 1000))
+ | PRT_DINIT3(div_round_up(sdram_params->ddr_freq/MHz
+ * 1000, 1000)), &ddr_publ_regs->ptr[2]);
switch (sdram_params->dramtype) {
case LPDDR3:
@@ -971,9 +971,9 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params)
printk(BIOS_INFO, "Starting SDRAM initialization...\n");
if ((sdram_params->dramtype == DDR3
- && sdram_params->ddr_freq > 800000000)
+ && sdram_params->ddr_freq > 800*MHz)
|| (sdram_params->dramtype == LPDDR3
- && sdram_params->ddr_freq > 533000000))
+ && sdram_params->ddr_freq > 533*MHz))
die("SDRAM frequency is to high!");
rkclk_configure_ddr(sdram_params->ddr_freq);