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authorjinkun.hong <jinkun.hong@rock-chips.com>2014-06-22 20:40:39 -0700
committerMarc Jones <marc.jones@se-eng.com>2015-03-16 04:52:46 +0100
commitac490b8a6bb31bf39fe8087ac3ba6a9b814beb87 (patch)
tree46a12e4bdf7cb7a82518ee09e70306701330124f /src/soc/rockchip/rk3288
parenta74d569731ab19a81a1c125b9d65659408649265 (diff)
downloadcoreboot-ac490b8a6bb31bf39fe8087ac3ba6a9b814beb87.tar.xz
coreboot: rk3288: Add a stub implementation of the rk3288 SOC
Most things still needs to be filled in, but this will allow us to build boards which use this SOC. BUG=chrome-os-partner:29778 TEST=emerge-veyron coreboot Original-Change-Id: If643d620c5fb8951faaf1ccde400a8e9ed7db3bc Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205069 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 2f72473a8c2b3fe21d77b351338e6209035878fb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I53fd0ced42f6ef191d7bf80d8b823bb880344239 Reviewed-on: http://review.coreboot.org/8653 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/rockchip/rk3288')
-rw-r--r--src/soc/rockchip/rk3288/Kconfig118
-rw-r--r--src/soc/rockchip/rk3288/Makefile.inc39
-rw-r--r--src/soc/rockchip/rk3288/addressmap.h102
-rw-r--r--src/soc/rockchip/rk3288/bootblock.c28
-rw-r--r--src/soc/rockchip/rk3288/cbmem.c29
-rw-r--r--src/soc/rockchip/rk3288/media.c27
-rw-r--r--src/soc/rockchip/rk3288/monotonic_timer.c40
-rw-r--r--src/soc/rockchip/rk3288/timer.c58
-rw-r--r--src/soc/rockchip/rk3288/timer.h43
-rw-r--r--src/soc/rockchip/rk3288/uart.c167
10 files changed, 651 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig
new file mode 100644
index 0000000000..51cf74ca65
--- /dev/null
+++ b/src/soc/rockchip/rk3288/Kconfig
@@ -0,0 +1,118 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config SOC_ROCKCHIP_RK3288
+ bool
+ default n
+ select ARCH_BOOTBLOCK_ARMV7
+ select ARCH_VERSTAGE_ARMV7
+ select ARCH_ROMSTAGE_ARMV7
+ select ARCH_RAMSTAGE_ARMV7
+ select CPU_HAS_BOOTBLOCK_INIT
+ select HAVE_MONOTONIC_TIMER
+ select HAVE_UART_MEMORY_MAPPED
+ select HAVE_UART_SPECIAL
+ select BOOTBLOCK_CONSOLE
+ select DYNAMIC_CBMEM
+
+if SOC_ROCKCHIP_RK3288
+
+config BOOTBLOCK_CPU_INIT
+ string
+ default "soc/rockchip/rk3288/bootblock.c"
+
+# ROM image layout.
+#
+# 0x00000 Combined bootblock and ID Block
+# 0x08000 Master CBFS header.
+# 0x18000 Free for CBFS data.
+#
+# iRAM (96k) layout.
+# (Note: The BootROM will jump to 0xff704004 after loading bootblock,
+# so the bootblock loading address must be at 0xff704004.)
+#
+# 0xFF70_0000 TTB (16KB).
+# 0xFF70_4004 Bootblock (max 16KB-4B).
+# 0xFF70_8000 ROM stage (max 40KB).
+# 0xFF71_2000 STACK (4KB).
+# 0xFF71_3000 CBFS mapping cache (20K)
+# 0xFF71_7FFF End of iRAM.
+
+config SYS_SDRAM_BASE
+ hex "SDRAM base address"
+ default 0x00000000
+
+config STACK_TOP
+ hex "STACK TOP"
+ default 0xff713000
+
+config STACK_BOTTOM
+ hex "STACK BOTTOM"
+ default 0xff712000
+
+config BOOTBLOCK_BASE
+ hex
+ default 0xff704004
+
+config ROMSTAGE_BASE
+ hex "ROM STAGE BASE"
+ default 0xff708000
+
+config RAMSTAGE_BASE
+ hex "RAMSTAGE BASE"
+ default 0x00200000
+
+config BOOTBLOCK_ROM_OFFSET
+ hex
+ default 0x0
+
+config CBFS_HEADER_ROM_OFFSET
+ hex
+ default 0x0008000
+
+config CBFS_ROM_OFFSET
+ hex
+ default 0x0018000
+
+config CBFS_SRAM_CACHE_ADDRESS
+ hex "sram memory address to put CBFS cache data"
+ default 0xff713000
+
+config CBFS_SRAM_CACHE_SIZE
+ hex "size of CBFS cache data"
+ default 0x00005000
+
+config CBFS_DRAM_CACHE_ADDRESS
+ hex "dram memory address to put CBFS cache data"
+ default 0x01000000
+
+config CBFS_DRAM_CACHE_SIZE
+ hex "size of CBFS cache data"
+ default 0x00100000
+
+config TTB_BUFFER
+ hex "memory address of the TTB buffer"
+ default 0xff700000
+
+config CONSOLE_SERIAL_UART_ADDRESS
+ hex
+ depends on CONSOLE_SERIAL_UART
+ default 0xFF690000
+
+endif
diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc
new file mode 100644
index 0000000000..50a1bbfcf6
--- /dev/null
+++ b/src/soc/rockchip/rk3288/Makefile.inc
@@ -0,0 +1,39 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+#bootblock-y += bootblock.c
+bootblock-y += cbmem.c
+bootblock-y += timer.c
+bootblock-y += monotonic_timer.c
+bootblock-y += media.c
+ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
+bootblock-$(CONFIG_DRIVERS_UART) += uart.c
+endif
+
+romstage-y += cbmem.c
+romstage-y += timer.c
+romstage-y += monotonic_timer.c
+romstage-y += media.c
+romstage-$(CONFIG_DRIVERS_UART) += uart.c
+
+ramstage-y += cbmem.c
+ramstage-y += timer.c
+ramstage-y += monotonic_timer.c
+ramstage-y += media.c
+ramstage-$(CONFIG_DRIVERS_UART) += uart.c
diff --git a/src/soc/rockchip/rk3288/addressmap.h b/src/soc/rockchip/rk3288/addressmap.h
new file mode 100644
index 0000000000..865e3c2ed1
--- /dev/null
+++ b/src/soc/rockchip/rk3288/addressmap.h
@@ -0,0 +1,102 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__
+#define __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__
+
+#define SDMMC1_BASE 0xFF0C0000
+#define SDMMC0_BASE 0xFF0D0000
+#define EMMC_BASE 0xFF0F0000
+#define SARADC_BASE 0xFF100000
+
+#define SPI0_BASE 0xFF110000
+#define SPI1_BASE 0xFF120000
+#define SPI2_BASE 0xFF130000
+
+#define I2C1_BASE 0xFF140000
+#define I2C3_BASE 0xFF150000
+#define I2C4_BASE 0xFF160000
+#define I2C5_BASE 0xFF170000
+#define UART0_BASE 0xFF180000
+#define UART1_BASE 0xFF190000
+#define DMAC_PERI_BASE 0xFF250000
+
+#define NANDC0_BASE 0xFF400000
+#define NANDC1_BASE 0xFF410000
+
+#define USB_HOST0_EHCI_BASE 0xFF500000
+#define USB_HOST0_OHCI_BASE 0xFF520000
+#define USB_HOST1_BASE 0xFF540000
+#define USB_OTG_BASE 0xFF580000
+
+#define DMAC_BUS_BASE 0xFF600000
+
+#define DDR_PCTL0_BASE 0xFF610000
+#define DDR_PCTL1_BASE 0xFF630000
+#define DDR_PUBL0_BASE 0xFF620000
+#define DDR_PUBL1_BASE 0xFF640000
+
+#define I2C0_BASE 0xFF650000
+#define I2C2_BASE 0xFF660000
+#define DW_PWM0123_BASE 0xFF670000
+#define RK_PWM0123_BASE 0xFF680000
+#define UART2_BASE 0xFF690000
+#define TIMER0_BASE 0xFF6B0000
+
+#define SRAM_BASE 0xFF700000
+#define PMU_BASE 0xFF730000
+#define GRF_SECURE_BASE 0xFF740000
+#define GPIO0_BASE 0xFF750000
+#define CRU_BASE 0xFF760000
+#define GRF_BASE 0xFF770000
+#define GPIO1_BASE 0xFF780000
+#define GPIO2_BASE 0xFF790000
+#define GPIO3_BASE 0xFF7A0000
+#define GPIO4_BASE 0xFF7B0000
+#define GPIO5_BASE 0xFF7C0000
+#define GPIO6_BASE 0xFF7D0000
+#define GPIO7_BASE 0xFF7E0000
+#define GPIO8_BASE 0xFF7F0000
+
+#define TIMER6_BASE 0xFF810000
+#define TIMER7_BASE 0xFF810020
+
+#define VOP_BIG_BASE 0xFF930000
+#define HDMI_TX_BASE 0xFF980000
+#define DMACS_BUS_BASE 0xFFB20000
+
+#define SERVICE_CORE_BASE 0xFFA80000
+#define SERVICE_DMA_BASE 0xFFA90000
+#define SERVICE_GPU_BASE 0xFFAA0000
+#define SERVICE_PERI_BASE 0xFFAB0000
+#define SERVICE_BUS_BASE 0xFFAC0000
+#define SERVICE_VIO_BASE 0xFFAD0000
+#define SERVICE_VPU_BASE 0xFFAE0000
+#define SERVICE_HEVC_BASE 0xFFAF0000
+
+#define EFUSE_BASE 0xFFB40000
+
+#define CORE_GICD_BASE 0xFFC01000
+#define CORE_GICC_BASE 0xFFC02000
+#define CPU_AXI_BUS_BASE 0xFFE00000
+
+#define BOOT_ROM_BASE 0xFFFF0000
+#define BOOT_ROM_CHIP_VER (BOOT_ROM+0x27F0)
+
+#endif /* __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ */
diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c
new file mode 100644
index 0000000000..9adf6ac242
--- /dev/null
+++ b/src/soc/rockchip/rk3288/bootblock.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/cache.h>
+#include <bootblock_common.h>
+#include "timer.h"
+
+static void bootblock_cpu_init(void)
+{
+ rk3288_init_timer();
+}
diff --git a/src/soc/rockchip/rk3288/cbmem.c b/src/soc/rockchip/rk3288/cbmem.c
new file mode 100644
index 0000000000..b29c87aaa5
--- /dev/null
+++ b/src/soc/rockchip/rk3288/cbmem.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stddef.h>
+#include <cbmem.h>
+
+#define FB_SIZE_MB 4
+void *cbmem_top(void)
+{
+ return (void *)(CONFIG_SYS_SDRAM_BASE +
+ (CONFIG_DRAM_SIZE_MB - FB_SIZE_MB)*MiB);
+}
+
diff --git a/src/soc/rockchip/rk3288/media.c b/src/soc/rockchip/rk3288/media.c
new file mode 100644
index 0000000000..75713eba7c
--- /dev/null
+++ b/src/soc/rockchip/rk3288/media.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <cbfs.h>
+#include <string.h>
+#include <console/console.h>
+
+int init_default_cbfs_media(struct cbfs_media *media)
+{
+ return 0;
+}
diff --git a/src/soc/rockchip/rk3288/monotonic_timer.c b/src/soc/rockchip/rk3288/monotonic_timer.c
new file mode 100644
index 0000000000..d33ed6858c
--- /dev/null
+++ b/src/soc/rockchip/rk3288/monotonic_timer.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <timer.h>
+#include <arch/io.h>
+#include "addressmap.h"
+#include "timer.h"
+
+static uint64_t timer_raw_value(void)
+{
+ uint64_t value0;
+ uint64_t value1;
+
+ value0 = (uint64_t)read32(&timer7_ptr->timer_curr_value0);
+ value1 = (uint64_t)read32(&timer7_ptr->timer_curr_value1);
+ value0 = value0 | value1<<32;
+ return value0;
+}
+
+void timer_monotonic_get(struct mono_time *mt)
+{
+ mono_time_set_usecs(mt, timer_raw_value() / clocks_per_usec);
+}
diff --git a/src/soc/rockchip/rk3288/timer.c b/src/soc/rockchip/rk3288/timer.c
new file mode 100644
index 0000000000..3a2c34d341
--- /dev/null
+++ b/src/soc/rockchip/rk3288/timer.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <timer.h>
+#include <delay.h>
+#include <arch/io.h>
+#include "timer.h"
+
+void init_timer(void)
+{
+}
+
+void rk3288_init_timer(void)
+{
+ write32(TIMER_LOAD_VAL, &timer7_ptr->timer_load_count0);
+ write32(TIMER_LOAD_VAL, &timer7_ptr->timer_load_count1);
+ write32(1, &timer7_ptr->timer_ctrl_reg);
+}
+
+/* delay x useconds */
+void udelay(unsigned usec)
+{
+ struct mono_time current, end;
+
+ timer_monotonic_get(&current);
+ end = current;
+ mono_time_add_usecs(&end, usec);
+
+ if (mono_time_after(&current, &end)) {
+ printk(BIOS_EMERG, "udelay: 0x%08x is impossibly large\n",
+ usec);
+ /* There's not much we can do if usec is too big. Use a long,
+ * paranoid delay value and hope for the best... */
+ end = current;
+ mono_time_add_usecs(&end, USECS_PER_SEC);
+ }
+
+ while (mono_time_before(&current, &end))
+ timer_monotonic_get(&current);
+}
+
diff --git a/src/soc/rockchip/rk3288/timer.h b/src/soc/rockchip/rk3288/timer.h
new file mode 100644
index 0000000000..8c72a4f373
--- /dev/null
+++ b/src/soc/rockchip/rk3288/timer.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __ROCKCHIP_RK3288_TIMER_H__
+#define __ROCKCHIP_RK3288_TIMER_H__
+
+#include "addressmap.h"
+
+#define SYS_CLK_FREQ 24000000
+static const uint32_t clocks_per_usec = SYS_CLK_FREQ/1000000;
+
+struct rk3288_timer {
+ u32 timer_load_count0;
+ u32 timer_load_count1;
+ u32 timer_curr_value0;
+ u32 timer_curr_value1;
+ u32 timer_ctrl_reg;
+ u32 timer_int_status;
+};
+
+static struct rk3288_timer * const timer7_ptr = (void *)TIMER7_BASE;
+
+#define TIMER_LOAD_VAL 0xffffffff
+
+void rk3288_init_timer(void);
+
+#endif /* __ROCKCHIP_RK3288_TIMER_H__ */
diff --git a/src/soc/rockchip/rk3288/uart.c b/src/soc/rockchip/rk3288/uart.c
new file mode 100644
index 0000000000..60b14a3209
--- /dev/null
+++ b/src/soc/rockchip/rk3288/uart.c
@@ -0,0 +1,167 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/uart.h>
+#include <arch/io.h>
+#include <boot/coreboot_tables.h>
+#include <console/console.h> /* for __console definition */
+#include <stdint.h>
+#include <drivers/uart/uart8250reg.h>
+
+/*
+ * TODO: Use DRIVERS_UART_8250MEM driver instead.
+ * There is an issue in the IO call functions where x86 and ARM
+ * ordering is reversed. This 8250MEM driver uses the x86 convention.
+ * This driver can be replaced once the IO calls are sorted.
+ */
+
+struct rk3288_uart {
+ union {
+ uint32_t thr; /* Transmit holding register. */
+ uint32_t rbr; /* Receive buffer register. */
+ uint32_t dll; /* Divisor latch lsb. */
+ };
+ union {
+ uint32_t ier; /* Interrupt enable register. */
+ uint32_t dlm; /* Divisor latch msb. */
+ };
+ union {
+ uint32_t iir; /* Interrupt identification register. */
+ uint32_t fcr; /* FIFO control register. */
+ };
+ uint32_t lcr; /* Line control register. */
+ uint32_t mcr; /* Modem control register. */
+ uint32_t lsr; /* Line status register. */
+ uint32_t msr; /* Modem status register. */
+ uint32_t scr;
+ uint32_t reserved1[(0x30 - 0x20) / 4];
+ uint32_t srbr[(0x70 - 0x30) / 4];
+ uint32_t far;
+ uint32_t tfr;
+ uint32_t rfw;
+ uint32_t usr;
+ uint32_t tfl;
+ uint32_t rfl;
+ uint32_t srr;
+ uint32_t srts;
+ uint32_t sbcr;
+ uint32_t sdmam;
+ uint32_t sfe;
+ uint32_t srt;
+ uint32_t stet;
+ uint32_t htx;
+ uint32_t dmasa;
+ uint32_t reserver2[(0xf4 - 0xac) / 4];
+ uint32_t cpr;
+ uint32_t ucv;
+ uint32_t ctr;
+} __attribute__ ((packed));
+
+
+static struct rk3288_uart * const uart_ptr =
+ (void *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
+
+static void rk3288_uart_tx_flush(void);
+static int rk3288_uart_tst_byte(void);
+
+static void rk3288_uart_init(void)
+{
+ /* FIXME: Use a hardcoded divisor for now.
+ * uint16_t divisor = (u16) uart_baudrate_divisor(default_baudrate(),
+ * uart_platform_refclk(), 16)
+ */
+ const unsigned divisor = 13;
+ const uint8_t line_config = UART8250_LCR_WLS_8; // 8n1
+
+ rk3288_uart_tx_flush();
+
+ // Disable interrupts.
+ writel(0, &uart_ptr->ier);
+ // Force DTR and RTS to high.
+ writel(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr);
+ // Set line configuration, access divisor latches.
+ writel(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr);
+ // Set the divisor.
+ writel(divisor & 0xff, &uart_ptr->dll);
+ writel((divisor >> 8) & 0xff, &uart_ptr->dlm);
+ // Hide the divisor latches.
+ writel(line_config, &uart_ptr->lcr);
+ // Enable FIFOs, and clear receive and transmit.
+ writel(UART8250_FCR_FIFO_EN |
+ UART8250_FCR_CLEAR_RCVR |
+ UART8250_FCR_CLEAR_XMIT, &uart_ptr->fcr);
+}
+
+static void rk3288_uart_tx_byte(unsigned char data)
+{
+ while (!(readl(&uart_ptr->lsr) & UART8250_LSR_THRE));
+ writel(data, &uart_ptr->thr);
+}
+
+static void rk3288_uart_tx_flush(void)
+{
+ while (!(readl(&uart_ptr->lsr) & UART8250_LSR_TEMT));
+}
+
+static unsigned char rk3288_uart_rx_byte(void)
+{
+ if (!rk3288_uart_tst_byte())
+ return 0;
+ return readl(&uart_ptr->rbr);
+}
+
+static int rk3288_uart_tst_byte(void)
+{
+ return (readl(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR;
+}
+
+
+
+void uart_init(int idx)
+{
+ rk3288_uart_init();
+}
+
+unsigned char uart_rx_byte(int idx)
+{
+ return rk3288_uart_rx_byte();
+}
+
+void uart_tx_byte(int idx, unsigned char data)
+{
+ rk3288_uart_tx_byte(data);
+}
+
+void uart_tx_flush(int idx)
+{
+ rk3288_uart_tx_flush();
+}
+
+#ifndef __PRE_RAM__
+void uart_fill_lb(void *data)
+{
+ struct lb_serial serial;
+ serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+ serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
+ serial.baud = default_baudrate();
+ lb_add_serial(&serial, data);
+
+ lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
+}
+#endif