diff options
| author | Lin Huang <hl@rock-chips.com> | 2016-06-28 14:19:18 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-12 00:27:39 +0200 |
| commit | 3d703bcc70c346ba1edad1b8f8391e62814f3ceb (patch) | |
| tree | 1218b20754422fff505fea51b0a7d66d585c63b6 /src/soc/rockchip/rk3399/clock.c | |
| parent | 10ea104476798641eff411d6ba61239c7c60a238 (diff) | |
| download | coreboot-3d703bcc70c346ba1edad1b8f8391e62814f3ceb.tar.xz | |
rockchip/rk3399: Use apll instead of apll_l define
Use the apll define instead of the apll_l define so it can be reused
when setting apll_b.
BRANCH=None
BUG=None
TEST=Boot from Gru
Change-Id: Iebc4ce3b66a86c33653292340b9855265ac4fc07
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: eb578110d19a35ef04f8749fdc202055abd50fd1
Original-Change-Id: I63966e98af48eaf49837eb0b781eea001a376ef4
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/356398
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Tested-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/15582
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/rockchip/rk3399/clock.c')
| -rw-r--r-- | src/soc/rockchip/rk3399/clock.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 8b274542c5..9388487672 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -47,12 +47,12 @@ static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); -static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); -static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); +static const struct pll_div apll_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); +static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); -static const struct pll_div *apll_l_cfgs[] = { - [APLL_L_1600_MHZ] = &apll_l_1600_cfg, - [APLL_L_600_MHZ] = &apll_l_600_cfg, +static const struct pll_div *apll_cfgs[] = { + [APLL_1600_MHZ] = &apll_1600_cfg, + [APLL_600_MHZ] = &apll_600_cfg, }; enum { @@ -487,16 +487,16 @@ void rkclk_init(void) HCLK_PERILP1_PLL_SEL_SHIFT)); } -void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq) +void rkclk_configure_cpu(enum apll_frequencies apll_l_freq) { u32 aclkm_div; u32 pclk_dbg_div; u32 atclk_div; u32 apll_l_hz; - apll_l_hz = apll_l_cfgs[apll_l_freq]->freq; + apll_l_hz = apll_cfgs[apll_l_freq]->freq; - rkclk_set_pll(&cru_ptr->apll_l_con[0], apll_l_cfgs[apll_l_freq]); + rkclk_set_pll(&cru_ptr->apll_l_con[0], apll_cfgs[apll_l_freq]); aclkm_div = div_round_up(apll_l_hz, ACLKM_CORE_HZ) - 1; |