diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-02-20 17:50:42 -0800 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2019-02-22 06:43:47 +0000 |
| commit | 314b5c370b4655bc701985ddf1d1d478067e7baa (patch) | |
| tree | 8c60a770ca6f6f2581626c1e6b6b4472c763b693 /src/soc/rockchip/rk3399/include | |
| parent | d1dfba4a1a790e2e30510c38dd9f3f0d9bab06b5 (diff) | |
| download | coreboot-314b5c370b4655bc701985ddf1d1d478067e7baa.tar.xz | |
rockchip/rk3399: Fix BL31 bootmem regions
The BL31 on RK3399 is split into multiple segments... the majority goes
into DRAM, but small parts must be put into SRAM and PMUSRAM. With
CB:31123 only the DRAM part was added to memlayout, so the SRAM parts
will not be correctly marked in bootmem and BL31 loading fails the
selfload check. This patch adds the remaining regions to fix the
problem.
Change-Id: Ia0597216c08512c47361a1dc0beb34d022a8994f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ting Shen <phoenixshen@google.com>
Diffstat (limited to 'src/soc/rockchip/rk3399/include')
| -rw-r--r-- | src/soc/rockchip/rk3399/include/soc/memlayout.ld | 4 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3399/include/soc/symbols.h | 27 |
2 files changed, 31 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index 01e352f230..73fc499d1c 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -30,11 +30,15 @@ SECTIONS SYMBOL(epmu_sram, 0xFF3B2000) SRAM_START(0xFF8C0000) +#if ENV_RAMSTAGE + REGION(bl31_sram, 0xFF8C0000, 64K, 1) +#else PRERAM_CBFS_CACHE(0xFF8C0000, 7K) TIMESTAMP(0xFF8C1C00, 1K) /* 0xFF8C2004 is the entry point address the masked ROM will jump to. */ OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 88K - 4) BOOTBLOCK(0xFF8D8000, 40K) +#endif VBOOT2_WORK(0XFF8E2000, 12K) TTB(0xFF8E5000, 24K) PRERAM_CBMEM_CONSOLE(0xFF8EB000, 8K) diff --git a/src/soc/rockchip/rk3399/include/soc/symbols.h b/src/soc/rockchip/rk3399/include/soc/symbols.h new file mode 100644 index 0000000000..f1487d0cb6 --- /dev/null +++ b/src/soc/rockchip/rk3399/include/soc/symbols.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_SYMBOLS_H__ +#define __SOC_SYMBOLS_H__ + +extern unsigned char _bl31_sram[]; +extern unsigned char _ebl31_sram[]; +#define _bl31_sram_size (_ebl31_sram - _bl31_sram) + +extern unsigned char _pmu_sram[]; +extern unsigned char _epmu_sram[]; +#define _pmu_sram_size (_epmu_sram - _pmu_sram) + +#endif |