diff options
| author | Lin Huang <hl@rock-chips.com> | 2017-11-02 17:53:30 +0800 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2017-11-28 19:15:31 +0000 |
| commit | 45f1b01324ed1712092e80fed7e03fe088452729 (patch) | |
| tree | 46c995f78dc384dd83bc240db25e3d36795c9371 /src/soc/rockchip/rk3399/include | |
| parent | 538b9ef66fc1e24274ae4da2fe9f45531e53a370 (diff) | |
| download | coreboot-45f1b01324ed1712092e80fed7e03fe088452729.tar.xz | |
rockchip/rk3399: mipi: properly configure PHY timing
These values are specified as constant time periods but the PHY
configuration is in terms of the current lane byte clock so using
constant values guarantees that the timings will be outside the
specification with some display configurations.
Derive the necessary configuration from the byte clock in order to
ensure that the PHY configuration is correct.
Change-Id: I396029956730907a33babe39c6a171f2fcea9dcd
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/rockchip/rk3399/include')
| -rw-r--r-- | src/soc/rockchip/rk3399/include/soc/mipi.h | 31 |
1 files changed, 21 insertions, 10 deletions
diff --git a/src/soc/rockchip/rk3399/include/soc/mipi.h b/src/soc/rockchip/rk3399/include/soc/mipi.h index 2ecd0ee19d..09285cf51c 100644 --- a/src/soc/rockchip/rk3399/include/soc/mipi.h +++ b/src/soc/rockchip/rk3399/include/soc/mipi.h @@ -233,16 +233,27 @@ check_member(rk_mipi_regs, dsi_int_msk1, 0xc8); #define THS_PRE_PROGRAM_EN BIT(7) #define THS_ZERO_PROGRAM_EN BIT(6) -#define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10 -#define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11 -#define PLL_LPF_AND_CP_CONTROL 0x12 -#define PLL_INPUT_DIVIDER_RATIO 0x17 -#define PLL_LOOP_DIVIDER_RATIO 0x18 -#define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19 -#define BANDGAP_AND_BIAS_CONTROL 0x20 -#define TERMINATION_RESISTER_CONTROL 0x21 -#define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22 -#define HS_RX_CONTROL_OF_LANE_0 0x44 +#define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10 +#define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11 +#define PLL_LPF_AND_CP_CONTROL 0x12 +#define PLL_INPUT_DIVIDER_RATIO 0x17 +#define PLL_LOOP_DIVIDER_RATIO 0x18 +#define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19 +#define BANDGAP_AND_BIAS_CONTROL 0x20 +#define TERMINATION_RESISTER_CONTROL 0x21 +#define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22 +#define HS_RX_CONTROL_OF_LANE_0 0x44 +#define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60 +#define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61 +#define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62 +#define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63 +#define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64 +#define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65 +#define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70 +#define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71 +#define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72 +#define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73 +#define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74 #define GEN_CMD_EMPTY BIT(0) #define GEN_CMD_FULL BIT(1) |