rockchip: rk3399: support basic clock driver

This patch initialize the PLL clocks and add function to
configure cpu freq. Right now, we set the little cpu freq to 600MHz.

In coreboot, we currently care about these four PLLs,
o. APLL for cpu clk, where A stands for AXI,
o. CPLL and GPLL are the generic PLL mainly for peripheral clk,
o. PPLL is only PMU clk.

For the peripheral clocks, there are thress clocks named as,
 aclk_perihp,
 aclk_perilp0,
 hclk_perilp1,
where the 'h' and 'l' letters refer to High and Low speed.
As the diagram below, the aclk_perihp always be the parent of
more higher speed peripheral devices like pcie, and
hclk_perilp1 for spi, i2c, aclk_perilp0 for crypto.
These three clocks can choose parent from GPLL or CPLL freely,
in this patch, they are all sourced from GPLL.

GPLL(594M)/CPLL(384M)                      APLL(600M for little core)
   |                                           |
   `-- aclk_perihp                             `-- clk_core(600M == APLL)
   |       |                                           |
   |       `-- periph_aclk(148.5M)                     `-- atclk_core(300M)
   |       `-- periph_hclk(148.5M)                     `-- aclkm_core(300M)
   |       `-- periph_pclk(37.125M)                    `-- pclk_dbg_core(100M)
   |
   `-- hclk_perilp1
   |       |
   |       `-- periph_hclk(99M)            PPLL(594M)
   |       `-- periph_pclk(49.5M)              |
   |                                           `-- pmu_pclk(99M)
   `-- aclk_perilp0
           |
           `-- periph_aclk(99M)
           `-- periph_hclk(99M)
           `-- periph_pclk(49.5M)

BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot

Change-Id: I1c46ff17e6b466529244afb41d7fd4abbcfd3da4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9f0d31177336a3450577950426f9cc9d56e2254c
Original-Change-Id: I4ad00df3e406bd0a7576287d6e62b8993a8c2d02
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332386
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14706
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

2 files changed, 87 insertions, 1 deletions

diff --git a/src/soc/rockchip/rk3399/include/soc/addressmap.h b/src/soc/rockchip/rk3399/include/soc/addressmap.h
index 377256ed29..427122c868 100644
--- a/src/soc/rockchip/rk3399/include/soc/addressmap.h
+++ b/src/soc/rockchip/rk3399/include/soc/addressmap.h
@@ -18,6 +18,7 @@
 
 #define PMUGRF_BASE		0xff320000
 #define PMUSGRF_BASE		0xff330000
+#define PMUCRU_BASE		0xff750000
 #define CRU_BASE		0xff760000
 #define GRF_BASE		0xff770000
 #define TIMER0_BASE		0xff850000
diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h
index c0ba52c4da..9b5479945d 100644
--- a/src/soc/rockchip/rk3399/include/soc/clock.h
+++ b/src/soc/rockchip/rk3399/include/soc/clock.h
@@ -16,6 +16,91 @@
 #ifndef __SOC_ROCKCHIP_RK3399_CLOCK_H__
 #define __SOC_ROCKCHIP_RK3399_CLOCK_H__
 
-void rkclk_configure_spi(unsigned int bus, unsigned int hz);
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct rk3399_pmucru_reg {
+	u32 ppll_con[6];
+	u32 reserved[0x1a];
+	u32 pmucru_clksel[6];
+	u32 pmucru_clkfrac_con[2];
+	u32 reserved2[0x18];
+	u32 pmucru_clkgate_con[3];
+	u32 reserved3;
+	u32 pmucru_softrst_con[2];
+	u32 reserved4[2];
+	u32 pmucru_rstnhold_con[2];
+	u32 reserved5[2];
+	u32 pmucru_gatedis_con[2];
+};
+check_member(rk3399_pmucru_reg, pmucru_gatedis_con[1], 0x134);
+
+struct rk3399_cru_reg {
+	u32 apll_l_con[6];
+	u32 reserved[2];
+	u32 apll_b_con[6];
+	u32 reserved1[2];
+	u32 dpll_con[6];
+	u32 reserved2[2];
+	u32 cpll_con[6];
+	u32 reserved3[2];
+	u32 gpll_con[6];
+	u32 reserved4[2];
+	u32 npll_con[6];
+	u32 reserved5[2];
+	u32 vpll_con[6];
+	u32 reserved6[0x0a];
+	u32 clksel_con[108];
+	u32 reserved7[0x14];
+	u32 clkgate_con[35];
+	u32 reserved8[0x1d];
+	u32 softrst_con[21];
+	u32 reserved9[0x2b];
+	u32 glb_srst_fst_value;
+	u32 glb_srst_snd_value;
+	u32 glb_cnt_th;
+	u32 misc_con;
+	u32 glb_rst_con;
+	u32 glb_rst_st;
+	u32 reserved10[0x1a];
+	u32 sdmmc_con[2];
+	u32 sdio0_con[2];
+	u32 sdio1_con[2];
+};
+check_member(rk3399_cru_reg, sdio1_con[1], 0x594);
+
+static struct rk3399_pmucru_reg * const pmucru_ptr = (void *)PMUCRU_BASE;
+static struct rk3399_cru_reg * const cru_ptr = (void *)CRU_BASE;
+
+#define OSC_HZ		(24*MHz)
+#define APLL_HZ		(600*MHz)
+#define GPLL_HZ		(594*MHz)
+#define CPLL_HZ		(384*MHz)
+#define PPLL_HZ		(594*MHz)
+
+#define PMU_PCLK_HZ	(99*MHz)
 
+#define ACLKM_CORE_HZ	(300*MHz)
+#define ATCLK_CORE_HZ	(300*MHz)
+#define PCLK_DBG_HZ	(100*MHz)
+
+#define PERIHP_ACLK_HZ	(148500*KHz)
+#define PERIHP_HCLK_HZ	(148500*KHz)
+#define PERIHP_PCLK_HZ	(37125*KHz)
+
+#define PERILP0_ACLK_HZ	(99000*KHz)
+#define PERILP0_HCLK_HZ	(99000*KHz)
+#define PERILP0_PCLK_HZ	(49500*KHz)
+
+#define PERILP1_HCLK_HZ	(99000*KHz)
+#define PERILP1_PCLK_HZ	(49500*KHz)
+
+enum apll_l_frequencies {
+	APLL_L_1600_MHZ,
+	APLL_L_600_MHZ,
+};
+
+void rkclk_init(void);
+void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq);
+void rkclk_configure_spi(unsigned int bus, unsigned int hz);
 #endif	/* __SOC_ROCKCHIP_RK3399_CLOCK_H__ */